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DTSTART:20260308T030000
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DTSTART:20251102T010000
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BEGIN:VEVENT
DTSTAMP:20251118T174612Z
UID:CF22ECD2-DA69-479A-889B-7C655EC512A4
DTSTART;TZID=America/Los_Angeles:20251104T083000
DTEND;TZID=America/Los_Angeles:20251104T153000
DESCRIPTION:IEEE EMC Chapter is sponsoring the event but no monetary gain i
 s gained or funded by the chapter.\n\nLocation: Cadence Design Systems\, B
 ldg 5\, 2655 Seely Ave.\, San Jose\, CA\n\nRegistration link will bring yo
 u to the options of the Paid workshop but also to the Free Exhibit/TC even
 ts\n\n2025 Silicon Valley Area Workshop on EMC Design of High-Speed System
 s workshop with Free Exhibit and Free IEEE EMC Technical Committee 10 on S
 ignal and Power Integrity meeting. For more details on the specific agenda
  including abstract and speakers&#39; bio\, go to https://drive.google.com/fil
 e/d/1oHHiBJtyebP1JgqafZF65pR9A0y145uA/view?usp=sharing\n\nAgenda: \nAgenda
 \nTable-top Vendor Exhibit in Lobby from 10:20 AM – 2:25 PM (FREE)\nVend
 ors are still signing up and already include Rohde and Schwarz\, PCB Autom
 ation\, Nexperia\, Cadence Design Systems\, PacketMicro\, and Clear Signal
  Solutions\n\n8:30 AM Light breakfast and registration\n9:00 AM Welcome re
 marks and introductions Electromagnetic Compatibility\n\n9:10 AM EMC Appli
 cations of 3D Printable Materials\nDr. Victor Khilkevich\, Missouri Univ. 
 of Sci. and Tech.\n\n9:45 AM Model-based EMC Analysis and Diagnosis toward
 s Design-for-EMC\nDr. Dipanjan Gope\, SimYog Technology and Indian Institu
 te of Science\n\n10:20 AM Break and vendor table-top show (FREE)\n\n10:45 
 AM Modeling ESD Protection for High-Speed Applications\nDr. Daryl Beetner\
 , Missouri Univ. of Sci. and Tech.\n\n11:20 AM Round Table Discussion - Fu
 ture directions and challenges in EMC\n\n11:50 AM Lunch\n\n12:50 PM Challe
 nges and Opportunity for Data Center Generation and Distributions\nDr. Zhi
 ping Yang\, PCB Automation\n\n1:25 PM Machine Learning-Assisted Power Deli
 very Network Design\nDr. Chulsoon Hwang\, Missouri Univ. of Sci. and Tech.
 \n\n2:00 PM Break and vendor table-top show (FREE)\n\n2:25 PM Challenges w
 ith next generation interconnect solutions\nStephen Scearce\, Amphenol\n\n
 3:00 PM Round Table Discussion - Future directions and challenges in SIPI 
 for High-\nSpeed Systems\n\n3:30 PM Happy Hour sponsored by Cadence Design
  Systems (FREE)\nIEEE EMC Mini Seminar-Paper Series Sponsored by IEEE EMC 
 Society Technical\nCommittee 10 on Signal and Power Integrity (FREE)\n\n3:
 30PM~4PM:  Machine Learn fro EMC/SI/PI-Blackbox\, Physics Recovery and Dec
 ision Making. by Lijun Jiang. Professor of MST\n\n4PM~4:30PM:  CVRM with F
 eedback for Platform PDN PI Design. by Kinger Cai of Arm\n\n4:30PM~5PM:   
 Developing an open S-parameter visualizer with assistance from AI. by Gior
 gi Maghlakelidze of nVidia.\n\n5PM~5:30PM:   Machine learning model for a 
 trace referenced to meshed ground planes. by Xiaoyan Xiong of Cadence.\n\n
 4:00 PM End of program\n\nBldg: 5\, 2655 Seely Ave.\, San Jose\, Californi
 a\, United States\, 95134
LOCATION:Bldg: 5\, 2655 Seely Ave.\, San Jose\, California\, United States\
 , 95134
ORGANIZER:caroline.chan.us@ieee.org
SEQUENCE:35
SUMMARY:2025 Silicon Valley Area Workshop on EMC Design of High-Speed Syste
 ms (PAID) + FREE Exhibits + FREE TC10 on Signal and Power Integrity mtg 
URL;VALUE=URI:https://events.vtools.ieee.org/m/508774
X-ALT-DESC:Description: &lt;br /&gt;&lt;p&gt;IEEE EMC Chapter is sponsoring the event b
 ut no monetary gain is gained or funded by the chapter.&lt;/p&gt;\n&lt;p&gt;Location: 
 Cadence Design Systems\, Bldg 5\, 2655 Seely Ave.\, San Jose\, CA&lt;/p&gt;\n&lt;p&gt;
 &amp;nbsp\;&lt;/p&gt;\n&lt;p&gt;Registration link will bring you to the options of the Pai
 d workshop but also to the Free Exhibit/TC events&lt;/p&gt;\n&lt;p&gt;2025 Silicon Val
 ley Area Workshop on EMC Design of High-Speed Systems workshop with Free E
 xhibit and Free IEEE EMC Technical Committee 10 on Signal and Power Integr
 ity meeting.&amp;nbsp\; For more details on the specific agenda including abst
 ract and speakers&#39; bio\, go to https://drive.google.com/file/d/1oHHiBJtyeb
 P1JgqafZF65pR9A0y145uA/view?usp=sharing&lt;/p&gt;&lt;br /&gt;&lt;br /&gt;Agenda: &lt;br /&gt;&lt;p&gt;Ag
 enda&lt;br&gt;Table-top Vendor Exhibit in Lobby from 10:20 AM &amp;ndash\; 2:25 PM (
 FREE)&lt;br&gt;Vendors are still signing up and already include Rohde and Schwar
 z\, PCB Automation\, Nexperia\, Cadence Design Systems\, PacketMicro\, and
  Clear Signal Solutions&lt;/p&gt;\n&lt;p&gt;&lt;br&gt;8:30 AM Light breakfast and registrati
 on&lt;br&gt;9:00 AM Welcome remarks and introductions Electromagnetic Compatibil
 ity&lt;/p&gt;\n&lt;p&gt;9:10 AM EMC Applications of 3D Printable Materials&lt;br&gt;Dr. Vict
 or Khilkevich\, Missouri Univ. of Sci. and Tech.&lt;/p&gt;\n&lt;p&gt;9:45 AM Model-bas
 ed EMC Analysis and Diagnosis towards Design-for-EMC&lt;br&gt;Dr. Dipanjan Gope\
 , SimYog Technology and Indian Institute of Science&lt;/p&gt;\n&lt;p&gt;10:20 AM Break
  and vendor table-top show (FREE)&lt;/p&gt;\n&lt;p&gt;&lt;br&gt;10:45 AM Modeling ESD Protec
 tion for High-Speed Applications&lt;br&gt;Dr. Daryl Beetner\, Missouri Univ. of 
 Sci. and Tech.&lt;/p&gt;\n&lt;p&gt;11:20 AM Round Table Discussion - Future directions
  and challenges in EMC&lt;/p&gt;\n&lt;p&gt;11:50 AM Lunch&lt;br&gt;&lt;br&gt;12:50 PM Challenges a
 nd Opportunity for Data Center Generation and Distributions&lt;br&gt;Dr. Zhiping
  Yang\, PCB Automation&lt;/p&gt;\n&lt;p&gt;1:25 PM Machine Learning-Assisted Power Del
 ivery Network Design&lt;br&gt;Dr. Chulsoon Hwang\, Missouri Univ. of Sci. and Te
 ch.&lt;/p&gt;\n&lt;p&gt;2:00 PM Break and vendor table-top show (FREE)&lt;/p&gt;\n&lt;p&gt;2:25 PM
  Challenges with next generation interconnect solutions&lt;br&gt;Stephen Scearce
 \, Amphenol&lt;/p&gt;\n&lt;p&gt;3:00 PM Round Table Discussion - Future directions and
  challenges in SIPI for High-&lt;br&gt;Speed Systems&lt;/p&gt;\n&lt;p&gt;3:30 PM Happy Hour 
 sponsored by Cadence Design Systems (FREE)&lt;br&gt;IEEE EMC Mini Seminar-Paper 
 Series Sponsored by IEEE EMC Society Technical&lt;br&gt;Committee 10 on Signal a
 nd Power Integrity (FREE)&lt;/p&gt;\n&lt;p class=&quot;MsoNormal&quot;&gt;3:30PM~4PM:&amp;nbsp\; &lt;st
 rong&gt;&amp;nbsp\;Machine Learn fro EMC/SI/PI-Blackbox\, Physics Recovery and De
 cision Making.&amp;nbsp\; &amp;nbsp\;&lt;/strong&gt;by Lijun Jiang. Professor of MST&lt;/p&gt;
 \n&lt;p class=&quot;MsoNormal&quot;&gt;&lt;strong&gt;&amp;nbsp\; &amp;nbsp\; &amp;nbsp\; &amp;nbsp\;&amp;nbsp\;&lt;/str
 ong&gt;4PM~4:30PM:&amp;nbsp\; &lt;strong&gt;&amp;nbsp\;CVRM with Feedback for Platform PDN 
 PI Design.&amp;nbsp\; &amp;nbsp\;&lt;/strong&gt;by Kinger Cai of Arm&lt;/p&gt;\n&lt;p class=&quot;MsoN
 ormal&quot;&gt;&amp;nbsp\; &amp;nbsp\; &amp;nbsp\; &amp;nbsp\; 4:30PM~5PM:&amp;nbsp\; &lt;strong&gt;&amp;nbsp\;&lt;
 /strong&gt;&amp;nbsp\;&lt;strong&gt;Developing an open S-parameter visualizer with assi
 stance from AI.&amp;nbsp\; &amp;nbsp\;&lt;/strong&gt;by Giorgi Maghlakelidze of&amp;nbsp\;nV
 idia.&lt;/p&gt;\n&lt;p class=&quot;MsoNormal&quot;&gt;&amp;nbsp\; &amp;nbsp\; &amp;nbsp\; &amp;nbsp\; 5PM~5:30PM
 :&amp;nbsp\;&amp;nbsp\;&lt;strong&gt;&amp;nbsp\;&lt;/strong&gt;&amp;nbsp\;&lt;strong&gt;Machine learning mod
 el for a trace referenced to meshed ground planes.&amp;nbsp\; &amp;nbsp\;&lt;/strong&gt;
 by Xiaoyan Xiong of Cadence.&lt;/p&gt;\n&lt;p&gt;4:00 PM End of program&lt;/p&gt;
END:VEVENT
END:VCALENDAR