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DESCRIPTION:Overview\n\nWe are pleased to welcome IEEE SSCS Distinguished L
 ecturer Pieter Harpe for a two-part presentation series focused on practic
 al and advanced techniques in analog-to-digital converter (ADC) design. Th
 e event will be hybrid\, with Pieter giving the talk from Eindhoven Univer
 sity of Technology\; however\, we are hosting an in-person watch party.\n\
 nFirst presentation: “Practical ADC Design Basics”\n\nThis first prese
 ntation provides a practical introduction to ADC design for beginners. Fro
 m a system perspective\, it illustrates how the overall ADC specifications
  can be established and the trade-offs at the system level. We’ll demons
 trate the process of selecting an ADC architecture and how the overall spe
 cifications trickle down to block- and circuit-level specifications. The r
 ole of a behavioral ADC model in investigating trade-offs and studying the
  impact of imperfections\, such as noise and mismatch\, will be explained.
  As an example\, we will follow this design process through transistor-lev
 el design and simulation of the individual components and ADC integration.
  It will be explained how to simulate each element\, and some practical at
 tention points will be detailed.\n\nSecond presentation: “ADC Enhancemen
 t Techniques in Advanced CMOS Technologies”\n\nThis second presentation 
 aims to introduce the basics and provide practical examples of advanced AD
 C enhancement techniques. With applications pushing for higher resolutions
  &amp; data-rates\, and technology scaling favoring digital design\, the use o
 f digital methods to enhance ADC performance is inevitable. This talk will
  first summarize trends and trade-offs in the use of these digital-intensi
 ve techniques before illustrating popular\, recent examples from the liter
 ature\, including calibration and enhancement techniques as well as digita
 lly inspired analog circuit design. Additionally\, an outlook on future ch
 allenges and opportunities in advanced CMOS technologies is provided.\n\n[
 ]\n\nSpeaker bio\n\nDr. Pieter Harpe received the MSc and PhD degrees from
  the Eindhoven University of Technology\, and then he worked for several y
 ears at imec on ultra-low-power ADCs. In 2011\, he joined Eindhoven Univer
 sity of Technology\, where he is currently an Associate Professor and the 
 leader of the Resource Efficient Electronics Lab. His main activities are 
 in low-power analog and mixed-signal circuits. Dr. Harpe is a TPC member f
 or ISSCC and A-SSCC\, Associate Editor for TCAS-I\, SSCS AdCom Member-at-L
 arge\, and SSCS Distinguished Lecturer. He also served as a Guest Editor f
 or JSSC and OJ-SSCS\, an ESSERC TPC member and subcom chair\, and an AACD 
 workshop organizer.\n\nSpeaker(s): Dr. Pieter Harpe\n\nAgenda: \nFirst pre
 sentation - “Practical ADC Design Basics”: 1:00 - 2:00 PM\n\nShort bre
 ak: 2:00 - 2:15 PM\n\nSecond presentation - “ADC Enhancement Techniques 
 in Advanced CMOS Technologies”: 2:15 - 3:15 PM\n\nQ&amp;A: 3:15 - 3:30 PM\n\
 n1 Broadway\, Cambridge\, Massachusetts\, United States\, 02142\, Virtual:
  https://events.vtools.ieee.org/m/510301
LOCATION:1 Broadway\, Cambridge\, Massachusetts\, United States\, 02142\, V
 irtual: https://events.vtools.ieee.org/m/510301
ORGANIZER:evan.merkel@ieee.org
SEQUENCE:34
SUMMARY:IEEE SSCS ADC Design Masterclass with DL Pieter Harpe
URL;VALUE=URI:https://events.vtools.ieee.org/m/510301
X-ALT-DESC:Description: &lt;br /&gt;&lt;p class=&quot;MsoNormal&quot; style=&quot;text-align: justi
 fy\; line-height: 115%\;&quot;&gt;&lt;strong&gt;&lt;span style=&quot;mso-ansi-language: EN-US\; 
 mso-no-proof: yes\;&quot;&gt;Overview&lt;/span&gt;&lt;/strong&gt;&lt;/p&gt;\n&lt;p class=&quot;MsoNormal&quot; st
 yle=&quot;text-align: justify\; line-height: 115%\;&quot;&gt;We are pleased to welcome 
 &lt;strong&gt;IEEE SSCS Distinguished Lecturer Pieter Harpe&lt;/strong&gt; for a two-p
 art presentation series focused on practical and advanced techniques in an
 alog-to-digital converter (ADC) design. The event will be hybrid\, with Pi
 eter giving the talk from Eindhoven University of Technology\; however\, w
 e are hosting an in-person watch party.&amp;nbsp\;&lt;/p&gt;\n&lt;p class=&quot;MsoNormal&quot; s
 tyle=&quot;text-align: justify\; line-height: 115%\;&quot;&gt;&lt;strong&gt;&lt;span style=&quot;mso-
 ansi-language: EN-US\; mso-no-proof: yes\;&quot;&gt;First presentation: &amp;ldquo\;Pr
 actical ADC Design Basics&amp;rdquo\;&lt;/span&gt;&lt;/strong&gt;&lt;/p&gt;\n&lt;p class=&quot;MsoNormal
 &quot; style=&quot;text-align: justify\; line-height: 115%\;&quot;&gt;&lt;span style=&quot;mso-bidi-
 font-family: Arial\; mso-ansi-language: EN-US\;&quot;&gt;This first presentation p
 rovides a practical introduction to ADC design for beginners. From a syste
 m perspective\, it illustrates how the overall ADC specifications can be e
 stablished and the trade-offs at the system level. We&amp;rsquo\;ll demonstrat
 e the process of selecting an ADC architecture and how the overall specifi
 cations trickle down to block- and circuit-level specifications. The role 
 of a behavioral ADC model in investigating trade-offs and studying the imp
 act of imperfections\, such as noise and mismatch\, will be explained. As 
 an example\, we will follow this design process through transistor-level d
 esign and simulation of the individual components and ADC integration. It 
 will be explained how to simulate each element\, and some practical attent
 ion points will be detailed.&lt;/span&gt;&lt;/p&gt;\n&lt;p class=&quot;MsoNormal&quot; style=&quot;text-
 align: justify\; line-height: 115%\;&quot;&gt;&lt;strong&gt;&lt;span style=&quot;mso-ansi-langua
 ge: EN-US\; mso-no-proof: yes\;&quot;&gt;Second presentation: &amp;ldquo\;ADC Enhancem
 ent Techniques in Advanced CMOS Technologies&amp;rdquo\;&lt;/span&gt;&lt;/strong&gt;&lt;/p&gt;\n
 &lt;p class=&quot;MsoNormal&quot; style=&quot;text-align: justify\; line-height: 115%\;&quot;&gt;&lt;sp
 an style=&quot;mso-bidi-font-family: Arial\; mso-ansi-language: EN-US\;&quot;&gt;This s
 econd presentation aims to introduce the basics and provide practical exam
 ples of advanced ADC enhancement techniques. With applications pushing for
  higher resolutions &amp;amp\; data-rates\, and technology scaling favoring di
 gital design\, the use of digital methods to enhance ADC performance is in
 evitable. This talk will first summarize trends and trade-offs in the use 
 of these digital-intensive techniques before illustrating popular\, recent
  examples from the literature\, including calibration and enhancement tech
 niques as well as digitally inspired analog circuit design. Additionally\,
  an outlook on future challenges and opportunities in advanced CMOS techno
 logies is provided.&lt;/span&gt;&lt;/p&gt;\n&lt;p class=&quot;MsoNormal&quot;&gt;&lt;span style=&quot;mso-ansi
 -language: EN-US\;&quot;&gt;&amp;nbsp\;&lt;/span&gt;&lt;/p&gt;\n&lt;p class=&quot;MsoNormal&quot;&gt;&lt;span style=&quot;
 mso-ansi-language: EN-US\;&quot;&gt;&lt;img src=&quot;https://events.vtools.ieee.org/vtool
 s_ui/media/display/7488e55c-e826-4a27-8262-80418b3977b2&quot; alt=&quot;&quot; width=&quot;184
 &quot; height=&quot;236&quot;&gt;&lt;/span&gt;&lt;/p&gt;\n&lt;h2&gt;&lt;span style=&quot;mso-ansi-language: EN-US\;&quot;&gt;S
 peaker bio&lt;/span&gt;&lt;/h2&gt;\n&lt;p class=&quot;MsoNormal&quot; style=&quot;text-align: justify\;&quot;
 &gt;&lt;span style=&quot;mso-ansi-language: EN-US\;&quot;&gt;Dr. Pieter Harpe received the MS
 c and PhD degrees from the Eindhoven University of Technology\, and then h
 e worked for several years at imec on ultra-low-power ADCs. In 2011\, he j
 oined Eindhoven University of Technology\, where he is currently an Associ
 ate Professor and the leader of the Resource Efficient Electronics Lab. Hi
 s main activities are in low-power analog and mixed-signal circuits. Dr. H
 arpe is a TPC member for ISSCC and A-SSCC\, Associate Editor for TCAS-I\, 
 SSCS AdCom Member-at-Large\, and SSCS Distinguished Lecturer. He also serv
 ed as a Guest Editor for JSSC and OJ-SSCS\, an ESSERC TPC member and subco
 m chair\, and an AACD workshop organizer.&lt;/span&gt;&lt;/p&gt;&lt;br /&gt;&lt;br /&gt;Agenda: &lt;b
 r /&gt;&lt;p class=&quot;MsoNormal&quot; style=&quot;text-align: justify\; line-height: 115%\;&quot;
 &gt;&lt;strong&gt;&lt;span style=&quot;mso-ansi-language: EN-US\; mso-no-proof: yes\;&quot;&gt;Firs
 t presentation - &amp;ldquo\;Practical ADC Design Basics&amp;rdquo\;: 1:00 - 2:00 
 PM&lt;/span&gt;&lt;/strong&gt;&lt;/p&gt;\n&lt;p class=&quot;MsoNormal&quot; style=&quot;text-align: justify\; 
 line-height: 115%\;&quot;&gt;&lt;strong&gt;&lt;span style=&quot;mso-ansi-language: EN-US\; mso-n
 o-proof: yes\;&quot;&gt;Short break: 2:00 - 2:15 PM&lt;/span&gt;&lt;/strong&gt;&lt;/p&gt;\n&lt;p class=
 &quot;MsoNormal&quot; style=&quot;text-align: justify\; line-height: 115%\;&quot;&gt;&lt;strong&gt;&lt;spa
 n style=&quot;mso-ansi-language: EN-US\; mso-no-proof: yes\;&quot;&gt;Second presentati
 on - &amp;ldquo\;ADC Enhancement Techniques in Advanced CMOS Technologies&amp;rdqu
 o\;: 2:15 - 3:15 PM&lt;/span&gt;&lt;/strong&gt;&lt;/p&gt;\n&lt;p class=&quot;MsoNormal&quot; style=&quot;text-
 align: justify\; line-height: 115%\;&quot;&gt;&lt;strong&gt;Q&amp;amp\;A: 3:15 - 3:30 PM&lt;/st
 rong&gt;&lt;/p&gt;
END:VEVENT
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