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DTSTART:20380118T221407
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DTSTART:19930206T230000
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DTSTAMP:20251128T180742Z
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DTSTART;TZID=America/Bogota:20251121T080000
DTEND;TZID=America/Bogota:20251121T150000
DESCRIPTION:This lecture will introduce advanced enhancement techniques for
  analog-to-digital converters (ADCs) in modern CMOS technologies. With inc
 reasing demands for higher resolution and data rates\, and continued techn
 ology scaling favoring digital design\, digital-assisted approaches have b
 ecome essential to improve ADC performance. The talk will overview recent 
 trends and trade-offs in digitally intensive converter design\, followed b
 y practical examples from literature covering calibration\, digital correc
 tion\, and digitally inspired analog circuit techniques. It will conclude 
 with perspectives on emerging challenges and opportunities for ADC design 
 in advanced CMOS nodes.\n\nSpeaker(s): Pieter Harpe\n\nBldg: Bienestar Pro
 \, Cl. 9 #27\, Bucaramaga\, Santander\, Colombia\, 650001
LOCATION:Bldg: Bienestar Pro\, Cl. 9 #27\, Bucaramaga\, Santander\, Colombi
 a\, 650001
ORGANIZER:nicolas.v@ieee.org
SEQUENCE:33
SUMMARY:ADC Enhancement Techniques in Advanced CMOS Technologies
URL;VALUE=URI:https://events.vtools.ieee.org/m/511015
X-ALT-DESC:Description: <br /><p>&nbsp\;</p>\n<p>This lecture will introduc
 e advanced enhancement techniques for analog-to-digital converters (ADCs) 
 in modern CMOS technologies. With increasing demands for higher resolution
  and data rates\, and continued technology scaling favoring digital design
 \, digital-assisted approaches have become essential to improve ADC perfor
 mance. The talk will overview recent trends and trade-offs in digitally in
 tensive converter design\, followed by practical examples from literature 
 covering calibration\, digital correction\, and digitally inspired analog 
 circuit techniques. It will conclude with perspectives on emerging challen
 ges and opportunities for ADC design in advanced CMOS nodes.</p>
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