BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:America/New_York BEGIN:DAYLIGHT DTSTART:20260308T030000 TZOFFSETFROM:-0500 TZOFFSETTO:-0400 RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3 TZNAME:EDT END:DAYLIGHT BEGIN:STANDARD DTSTART:20251102T010000 TZOFFSETFROM:-0400 TZOFFSETTO:-0500 RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11 TZNAME:EST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20251203T101525Z UID:F281917E-7A89-4911-A4F6-19668CF7B7A2 DTSTART;TZID=America/New_York:20251128T100000 DTEND;TZID=America/New_York:20251128T120000 DESCRIPTION:Abstract:\n\nData center\, compute\, and AI applications contin ue to demand higher bandwidth from electrical interconnects. The volume of short-reach links (less than a few cm) has exploded to facilitate high-ba ndwidth data movement between compute engines and memory in the AI era. Th is massive growth will continue as the industry moves towards highly-paral lelized die-to-die interfaces to support chiplet-based architectures. Howe ver\, power efficiency in these links is of paramount importance to mainta in reasonable power levels within a compute drawer. This talk will focus o n trends and advancements in power-efficient short reach links that aim to maximize the shoreline bandwidth density. Multi-disciplinary approaches i nvolving circuit innovations\, architectural advancements\, data signaling techniques\, and packaging technologies are required to deliver linear ba ndwidth densities above 1 Tbps/mm at power efficiencies below 500 fJ/bit.\ n\nTimothy (Tod) Dickson received the B.S. and M.Eng. degrees from the Uni versity of Florida\, and the Ph.D. degree from the University of Toronto. Since 2006 he has been with the IBM T.J. Watson Research Center in Yorktow n Heights\, NY where he is currently a Principal Research Scientist. His r esearch is on circuits and architectures for power-efficient serial commun ication. He is also an Adjunct Professor at Columbia University in New Yor k\, NY.\n\nDr. Dickson has been an author or co-author of several papers t hat have received best paper awards\, including the inaugural VLSI Circuit s Symposium Best Student Paper Award in 2004\, the IEEE Journal of Solid-S tate Circuits Best Paper in 2009\, the ISSCC Beatrice Winner Award in 2009 \, and the IEEE CICC Best Regular Paper Award in 2015 and Best Invited Pap er Award in 2024. He served on the TPC of the IEEE CICC from 2017-2023 and was an Associate Editor of the IEEE Solid State Circuits Letters over the same time period. He is currently an Associate Editor of the IEEE Open Jo urnal of the Solid State Circuits Society and IEEE SSCS Distinguished Lect urer. He is an IEEE Senior Member.\n\nRoom: 2.184\, Bldg: EV building\, 15 15 Ste-Catherine Street W\, Montreal\, Quebec\, Canada\, H3G1M8 LOCATION:Room: 2.184\, Bldg: EV building\, 1515 Ste-Catherine Street W\, Mo ntreal\, Quebec\, Canada\, H3G1M8 ORGANIZER:glenn.cowan@concordia.ca SEQUENCE:13 SUMMARY:IEEE SSCS DL: Power-Efficient Short-Reach Electrical Links for the AI Era URL;VALUE=URI:https://events.vtools.ieee.org/m/511492 X-ALT-DESC:Description: <br /><p class="MsoNormal"><strong><span lang="EN-U S">Abstract:</span></strong></p>\n<p class="MsoNormal"><span lang="EN-US"> Data center\, compute\, and AI applications continue to demand higher band width from electrical interconnects. The volume of short-reach links (less than a few cm) has exploded to facilitate high-bandwidth data movement be tween compute engines and memory in the AI era. This massive growth will c ontinue as the industry moves towards highly-parallelized die-to-die inter faces to support chiplet-based architectures. However\, power efficiency i n these links is of paramount importance to maintain reasonable power leve ls within a compute drawer. This talk will focus on trends and advancement s in power-efficient short reach links that aim to maximize the shoreline bandwidth density. Multi-disciplinary approaches involving circuit innovat ions\, architectural advancements\, data signaling techniques\, and packag ing technologies are required to deliver linear bandwidth densities above 1 Tbps/mm at power efficiencies below 500 fJ/bit.</span></p>\n<p class="Ms oNormal"><strong><span lang="EN-US">Timothy (Tod) Dickson</span></strong>< strong> </strong><span lang="EN-US">received the B.S. and M.Eng. degrees f rom the University of Florida\, and the Ph.D. degree from the University o f Toronto. Since 2006 he has been with the IBM T.J. Watson Research Center in Yorktown Heights\, NY where he is currently a Principal Research Scien tist. His research is on circuits and architectures for power-efficient se rial communication. He is also an Adjunct Professor at Columbia University in New York\, NY.</span></p>\n<p><span lang="EN-US">Dr. Dickson has been an author or co-author of several papers that have received best paper awa rds\, including the inaugural VLSI Circuits Symposium Best Student Paper A ward in 2004\, the IEEE Journal of Solid-State Circuits Best Paper in 2009 \, the ISSCC Beatrice Winner Award in 2009\, and the IEEE CICC Best Regula r Paper Award in 2015 and Best Invited Paper Award in 2024. He served on t he TPC of the IEEE CICC from 2017-2023 and was an Associate Editor of the IEEE Solid State Circuits Letters over the same time period. He is current ly an Associate Editor of the IEEE Open Journal of the Solid State Circuit s Society and IEEE SSCS Distinguished Lecturer. He is an IEEE Senior Membe r.</span></p> END:VEVENT END:VCALENDAR