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DTSTAMP:20251110T220257Z
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DTSTART;TZID=Pacific/Auckland:20251110T190000
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DESCRIPTION:The IEEE Women in Engineering New Zealand North Section invites
  you to a technical webinar with Ras Attale\, a Senior Hardware Engineer a
 t Siemens\, with nearly seven years of experience on the team. Previously 
 worked at Arm\, contributing to their verification team in Cortex A. Also 
 currently pursuing a Master’s in Cybersecurity at the University of Oxfo
 rd.\n\nThe webinar will discuss a comprehensive framework for scalable ver
 ification of complex system-on-chip (SoC) designs. This solution addresses
  the growing challenges of verification complexity through reusable test p
 lans that maximize component and protocol reusability across multiple IP b
 locks. The framework implements requirement-driven verification to ensure 
 complete traceability between design requirements and the verification pro
 cess. Real-time interactive dashboards with AI features deliver immediate 
 visibility into verification progress\, enabling early bug detection\, opt
 imized resource allocation\, and data-driven decision making. The methodol
 ogy employs systematic coverage collection and closure techniques\, includ
 ing a traffic light system for waivers\, while emphasizing the importance 
 of creating detailed verification test plans linked to design requirements
  from project inception. Through this Metric Driven Verification approach\
 , the Tessent Embedded Analytics verification flow helps engineering teams
  manage complex verification environments more efficiently.\n\nCo-sponsore
 d by: University of Auckland\n\nSpeaker(s): \, Ras\n\nVirtual: https://eve
 nts.vtools.ieee.org/m/512325
LOCATION:Virtual: https://events.vtools.ieee.org/m/512325
ORGANIZER:thiaza.thasthakeer@gmail.com
SEQUENCE:34
SUMMARY:Scalable Verification Framework for Complex System-on-Chip Designs
URL;VALUE=URI:https://events.vtools.ieee.org/m/512325
X-ALT-DESC:Description: <br /><p>The IEEE Women in Engineering New Zealand 
 North Section invites you to a technical webinar with Ras Attale\, a Senio
 r Hardware Engineer at Siemens\, with nearly seven years of experience on 
 the team. Previously worked at Arm\, contributing to their verification te
 am in Cortex A. Also currently pursuing a Master&rsquo\;s in Cybersecurity
  at the University of Oxford.</p>\n<p>The webinar will discuss a comprehen
 sive framework for scalable verification of complex system-on-chip (SoC) d
 esigns. This solution addresses the growing challenges of verification com
 plexity through reusable test plans that maximize component and protocol r
 eusability across multiple IP blocks. The framework implements requirement
 -driven verification to ensure complete traceability between design requir
 ements and the verification process. Real-time interactive dashboards with
  AI features deliver immediate visibility into verification progress\, ena
 bling early bug detection\, optimized resource allocation\, and data-drive
 n decision making. The methodology employs systematic coverage collection 
 and closure techniques\, including a traffic light system for waivers\, wh
 ile emphasizing the importance of creating detailed verification test plan
 s linked to design requirements from project inception. Through this Metri
 c Driven Verification approach\, the Tessent Embedded Analytics verificati
 on flow helps engineering teams manage complex verification environments m
 ore efficiently.</p>
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