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DESCRIPTION:Hardware Fuzzing: What? Why? How?\nDr. Jeyavijayan (JV) Rajendr
 an\nAssociate Professor\, Department of Electrical and Computer Engineerin
 g\, Texas A&amp;M University\n\nAbstract: Hardware is at the heart of computin
 g systems. However\, recent years have seen increased attacks exploiting h
 ardware vulnerabilities and exploits\, which even traditional software-bas
 ed protections cannot prevent. Hardware fuzzing has shown promise in detec
 ting vulnerabilities in large-scale designs like modern processors. In thi
 s talk\, I will describe the hardware vulnerabilities in hardware descript
 ion languages\, such as Verilog and VHDL. Then\, I will explain a new and 
 radical approach called hardware fuzzing to find these vulnerabilities and
  detail how fuzzing techniques can be combined with existing formal verifi
 cation techniques to detect vulnerabilities efficiently. Finally\, I will 
 discuss a strategy for pinpointing vulnerabilities to accelerate the mitig
 ation process and briefly talk about improving the efficiency of hardware 
 fuzzing using ML/AI techniques\, such as multi-armed bandit (MAB) and larg
 e language models (LLM).\n\nBiography: Dr. Jeyavijayan (JV) Rajendran is a
 n Associate Professor and an ASCEND Fellow in the Department of Electrical
  and Computer Engineering at Texas A&amp;M University. He obtained his Ph.D. d
 egree from New York University in August 2015. His research interests incl
 ude hardware security and computer security. His research has won the NSF 
 CAREER Award in 2017\, the ONR Young Investigator Award in 2022\, the IEEE
  CEDA Ernest Kuh Early Career Award in 2021\, the ACM SIGDA Outstanding Yo
 ung Faculty Award in 2019\, the Intel Academic Leadership Award\, along wi
 th several best student paper awards and best PhD dissertation awards. He 
 is also an alumnus of the National Academy of Engineering’s Frontiers of
  Engineering\, 2023\, and serves on NASEM/NAE committees. He organizes and
  has co‐founded Hack@DAC\, a student security competition co-located wit
 h DAC and SUSHI.\n\n[]\n\nCo-sponsored by: IEEE\, Rochester Section\, Regi
 on 1\n\nAgenda: \nTuesday\, November 25\, 2025:\n\n7:00 PM EST - Welcome\n
 \n7:05 PM EST - Webinar by Dr. Dr. Jeyavijayan (JV) Rajendran\n\n7:50 PM E
 ST - Q&amp;A\n\n8:00 PM EST - End of Webinar\n\nVirtual: https://events.vtools
 .ieee.org/m/512380
LOCATION:Virtual: https://events.vtools.ieee.org/m/512380
ORGANIZER:cemeec@rit.edu
SEQUENCE:26
SUMMARY:Hardware Fuzzing: What? Why? How?
URL;VALUE=URI:https://events.vtools.ieee.org/m/512380
X-ALT-DESC:Description: &lt;br /&gt;&lt;div style=&quot;text-align: center\;&quot; data-olk-co
 py-source=&quot;MessageBody&quot;&gt;&lt;span style=&quot;text-decoration: underline\;&quot;&gt;&lt;strong
 &gt;Hardware Fuzzing: What? Why? How?&lt;/strong&gt;&lt;/span&gt;&lt;/div&gt;\n&lt;div style=&quot;text
 -align: center\;&quot; data-olk-copy-source=&quot;MessageBody&quot;&gt;Dr. Jeyavijayan (&lt;spa
 n class=&quot;markkjhleiwnb&quot; data-markjs=&quot;true&quot; data-ogac=&quot;&quot; data-ogab=&quot;&quot; data-
 ogsc=&quot;&quot; data-ogsb=&quot;&quot;&gt;JV&lt;/span&gt;) Rajendran&lt;/div&gt;\n&lt;div style=&quot;text-align: c
 enter\;&quot; data-olk-copy-source=&quot;MessageBody&quot;&gt;Associate Professor\, Departme
 nt of Electrical and Computer Engineering\, Texas A&amp;amp\;M University&lt;/div
 &gt;\n&lt;div style=&quot;text-align: justify\;&quot; data-olk-copy-source=&quot;MessageBody&quot;&gt;&lt;
 br&gt;&lt;br&gt;&lt;strong&gt;Abstract&lt;/strong&gt;:&amp;nbsp\; Hardware is at the heart of compu
 ting systems. However\, recent years have seen increased attacks exploitin
 g hardware vulnerabilities and exploits\, which even traditional software-
 based protections cannot prevent. Hardware fuzzing has shown promise in de
 tecting vulnerabilities in large-scale designs like modern processors. In 
 this talk\, I will describe the hardware vulnerabilities in hardware descr
 iption languages\, such as Verilog and VHDL. Then\, I will explain a new a
 nd radical approach called hardware fuzzing to find these vulnerabilities 
 and detail how fuzzing techniques can be combined with existing formal ver
 ification techniques to detect vulnerabilities efficiently. Finally\, I wi
 ll discuss a strategy for pinpointing vulnerabilities to accelerate the mi
 tigation process and briefly talk about improving the efficiency of hardwa
 re fuzzing using ML/AI techniques\, such as multi-armed bandit (MAB) and l
 arge language models (LLM).&lt;br&gt;&lt;br&gt;&lt;/div&gt;\n&lt;div&gt;&lt;strong&gt;Biography&lt;/strong&gt;
 :&amp;nbsp\; Dr. Jeyavijayan (&lt;span class=&quot;markkjhleiwnb&quot; data-markjs=&quot;true&quot; d
 ata-ogac=&quot;&quot; data-ogab=&quot;&quot; data-ogsc=&quot;&quot; data-ogsb=&quot;&quot;&gt;JV&lt;/span&gt;) Rajendran is
  an Associate Professor and an ASCEND Fellow in the Department of Electric
 al and Computer Engineering at Texas A&amp;amp\;M University. He obtained his 
 Ph.D. degree from New York University in August 2015. His research interes
 ts include hardware security and computer security. His research has won t
 he NSF CAREER Award in 2017\, the ONR Young Investigator Award in 2022\, t
 he IEEE CEDA Ernest Kuh Early Career Award in 2021\, the ACM SIGDA Outstan
 ding Young Faculty Award in 2019\, the Intel Academic Leadership Award\, a
 long with several best student paper awards and best PhD dissertation awar
 ds. He is also an alumnus of the National Academy of Engineering&amp;rsquo\;s 
 Frontiers of Engineering\, 2023\, and serves on NASEM/NAE committees. He o
 rganizes and has co‐founded Hack@DAC\, a student security competition co
 -located with DAC and SUSHI.&lt;/div&gt;\n&lt;div&gt;&amp;nbsp\;&lt;/div&gt;\n&lt;div&gt;&lt;img src=&quot;htt
 ps://events.vtools.ieee.org/vtools_ui/media/display/46130fdf-6681-4653-85e
 5-8eea7383afe7&quot; alt=&quot;&quot; width=&quot;150&quot; height=&quot;200&quot;&gt;&lt;/div&gt;&lt;br /&gt;&lt;br /&gt;Agenda: 
 &lt;br /&gt;&lt;p&gt;&lt;span style=&quot;text-decoration: underline\;&quot;&gt;Tuesday\, November 25\
 , 2025&lt;/span&gt;:&lt;/p&gt;\n&lt;p&gt;7:00 PM EST - Welcome&lt;/p&gt;\n&lt;p&gt;7:05 PM EST - Webinar
  by Dr. Dr. Jeyavijayan (&lt;span class=&quot;markkjhleiwnb&quot; data-markjs=&quot;true&quot; da
 ta-ogac=&quot;&quot; data-ogab=&quot;&quot; data-ogsc=&quot;&quot; data-ogsb=&quot;&quot;&gt;JV&lt;/span&gt;) Rajendran&lt;/p&gt;
 \n&lt;p&gt;7:50 PM EST - Q&amp;amp\;A&lt;/p&gt;\n&lt;p&gt;8:00 PM EST - End of Webinar&lt;/p&gt;
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