BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:America/Los_Angeles BEGIN:DAYLIGHT DTSTART:20260308T030000 TZOFFSETFROM:-0800 TZOFFSETTO:-0700 RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3 TZNAME:PDT END:DAYLIGHT BEGIN:STANDARD DTSTART:20251102T010000 TZOFFSETFROM:-0700 TZOFFSETTO:-0800 RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11 TZNAME:PST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20251206T154353Z UID:45F07FBB-7E2B-40AA-9747-D09BBF03DF01 DTSTART;TZID=America/Los_Angeles:20251204T160000 DTEND;TZID=America/Los_Angeles:20251204T183000 DESCRIPTION:TALK #1 by Vanessa Chen\nTITLE\nAI-Enhanced RF/Mixed-Signal Cir cuits for Reliable Operations\n\nABSTRACT\nAI-driven design and optimizati on are revolutionizing RF and mixed-signal circuits for operation in extre me environments\, including high radiation and wide temperature ranges. Th is talk explores the use of reinforcement learning (RL) and generative mod els to improve circuit robustness and adaptability. RL-based self-healing techniques leverage embedded electromagnetic sensors for real-time monitor ing and dynamic fault recovery while generative models accelerate design s pace exploration\, enabling resilient and efficient circuit topologies. Th e presentation will highlight AI-enhanced designs such as adaptive power a mplifiers\, PMICs\, and multispectral sensors that enhance performance and reliability in harsh environments.\n\nBIOGRAPHY\nVanessa Chen received he r Ph.D. in Electrical and Computer Engineering from Carnegie Mellon Univer sity in 2013\, where she worked on energy-efficient\, ultra-high-speed ADC s with real-time calibration and interned at IBM T. J. Watson Research Cen ter. She previously held circuit design roles at Qualcomm in San Diego and Realtek in Taiwan\, focusing on self-healing RF and mixed-signal circuits . Her research explores AI-enhanced circuits and systems\, including intel ligent sensory interfaces\, RF/mixed-signal hardware security\, and ubiqui tous sensing and computing. Dr. Chen is a recipient of the NSF CAREER Awar d\, the CMU College of Engineering Dean’s Early Career Fellowship\, and the IBM PhD Fellowship. She has served on program committees for ISSCC\, V LSI\, CICC\, A-SSCC\, and DAC\, as an Associate Editor for several IEEE jo urnals\, and is currently an IEEE SSCS Distinguished Lecturer for 2025–2 026.\n\nTALK #2 by Tim Hollis\n\nTITLE\nMemory Interfaces – Past\, Prese nt and Future\n\nABSTRACT\n\nDRAM standards have evolved tremendously over the last two-and-a-half decades\, leading to diversification not only in the architecture of the memory array but also in that of the off-chip inte rface. Application-specific signaling channels have influenced the transce iver design nearly as much as system power and bandwidth requirements have . The influence of the multidrop server channel\, along with a broad range of target environments\, has led the DDR branch of JEDEC DRAMs to incorpo rate multi tap Decision Feedback Equalization to maximize flexibility\, wh ile shrinking supply voltages to facilitate energy reduction have led Low- Power DDR (LPDDR) to completely rethink the output driver structure. In pa rallel\, Graphics DDR (GDDR) has reached speeds requiring nearly equal car e of the external channel and the chip itself. The adoption of multi-level signaling in GDDR6x and GDDR7 to relax on-chip frequency requirements has only heightened the need for more rigorous co-design of transceiver\, pac kage and system characteristics. And\, of course\, the integration of sili con interposers to support High Bandwidth Memory (HBM) has driven a paradi gm shift in memory interface design. With all of these adaptations\, and m any others not captured here\, the splintering DRAM family continues to pu sh the boundaries of single-ended signaling into the future. This presenta tion briefly explores what has driven the diversification in DRAM signalin g schemes over the decades\, will discuss the motivation behind present em bodiments\, and will project into the future to where the DRAM interface i s likely headed (e.g.\, features and functions necessary for continued ene rgy-efficient bandwidth scaling).\n\nBIOGRAPHY\n\nTim Hollis received the Ph.D. degree in electrical engineering from Brigham Young University\, Pro vo\, UT\, USA\, in 2007. In 2006\, he joined the Advanced Architecture Gro up at Micron Technology in Boise\, Idaho\, USA where he contributed to sev eral pathfinding activities including the first-generation Hybrid Memory C ube. From 2012 to 2014\, he worked as a chipset architect at Qualcomm in S an Diego\, CA\, USA. He returned to Micron in 2014\, where he currently le ads the Interface Pathfinding Group as a Micron Fellow. He has published 1 8 articles in journals\, conference proceedings\, and technical magazines\ , and holds 274 issued U.S. and international patents. Dr. Hollis served a s a member of the IEEE Workshop on Microelectronics and Electron Devices O rganizing Committee from 2010-2024\, including the General Chair in 2013. He has served on other IEEE conference committees as well as DesignCon’s Technical Program Committee from 2013 to 2015. From 2017 to 2020 he serve d as the Technology Editor for the IEEE Solid-State Circuits Magazine and as a Guest Editor for memory- and interface-related special issues in 2016 and 2019\, respectively.\n\nSpeaker(s): Dr. Vanessa Chen\, Dr. Tim Hollis \n\nBldg: Qualcomm Q Auditorium\, 6455 Lusk Blvd\, San Diego\, CA 92121\, San Diego\, California\, United States\, 92130\, Virtual: https://events.v tools.ieee.org/m/516118 LOCATION:Bldg: Qualcomm Q Auditorium\, 6455 Lusk Blvd\, San Diego\, CA 9212 1\, San Diego\, California\, United States\, 92130\, Virtual: https://even ts.vtools.ieee.org/m/516118 ORGANIZER:jfshi@ieee.org SEQUENCE:12 SUMMARY:IEEE APS/CASS/EDS/MTTS/SSCS Double-Feature DL Seminars\, by Vanessa Chen (Carnegie Mellon Univ.) & Tim Hollis (Micron)\, Dec. 4 @ 4pm PST URL;VALUE=URI:https://events.vtools.ieee.org/m/516118 X-ALT-DESC:Description: <br /><div>\n<div>\n<div><strong>TALK #1 by Vanessa Chen</strong></div>\n<div>&nbsp\;</div>\nTITLE</div>\n</div>\n<div>AI-Enh anced RF/Mixed-Signal Circuits for Reliable Operations</div>\n<div>&nbsp\; </div>\n<div>ABSTRACT</div>\n<div>AI-driven design and optimization are re volutionizing RF and mixed-signal circuits for operation in extreme enviro nments\, including high radiation and wide temperature ranges. This talk e xplores the use of reinforcement learning (RL) and generative models to im prove circuit robustness and adaptability. RL-based self-healing technique s leverage embedded electromagnetic sensors for real-time monitoring and d ynamic fault recovery while generative models accelerate design space expl oration\, enabling resilient and efficient circuit topologies. The present ation will highlight AI-enhanced designs such as adaptive power amplifiers \, PMICs\, and multispectral sensors that enhance performance and reliabil ity in harsh environments.</div>\n<div>&nbsp\;</div>\n<div>BIOGRAPHY</div> \n<div>Vanessa Chen received her Ph.D. in Electrical and Computer Engineer ing from Carnegie Mellon University in 2013\, where she worked on energy-e fficient\, ultra-high-speed ADCs with real-time calibration and interned a t IBM T. J. Watson Research Center. She previously held circuit design rol es at Qualcomm in San Diego and Realtek in Taiwan\, focusing on self-heali ng RF and mixed-signal circuits. Her research explores AI-enhanced circuit s and systems\, including intelligent sensory interfaces\, RF/mixed-signal hardware security\, and ubiquitous sensing and computing. Dr. Chen is a r ecipient of the NSF CAREER Award\, the CMU College of Engineering Dean&rsq uo\;s Early Career Fellowship\, and the IBM PhD Fellowship. She has served on program committees for ISSCC\, VLSI\, CICC\, A-SSCC\, and DAC\, as an Associate Editor for several IEEE journals\, and is currently an IEEE SSCS Distinguished Lecturer for 2025&ndash\;2026.</div>\n<div>&nbsp\;</div>\n< div><strong>TALK #2 by Tim Hollis</strong></div>\n<div>&nbsp\;</div>\n<div >TITLE</div>\n<div>Memory Interfaces &ndash\; Past\, Present and Future</d iv>\n<div>&nbsp\;</div>\n<div>ABSTRACT</div>\n<div>\n<p class="MsoNormal"> DRAM standards have evolved tremendously over the last two-and-a-half deca des\, leading to diversification not only in the architecture of the memor y array but also in that of the off-chip interface. Application-specific s ignaling channels have influenced the transceiver design nearly as much as system power and bandwidth requirements have. The influence of the multid rop server channel\, along with a broad range of target environments\, has led the DDR branch of JEDEC DRAMs to incorporate multi tap Decision Feedb ack Equalization to maximize flexibility\, while shrinking supply voltages to facilitate energy reduction have led Low-Power DDR (LPDDR) to complete ly rethink the output driver structure. In parallel\, Graphics DDR (GDDR) has reached speeds requiring nearly equal care of the external channel and the chip itself. The adoption of multi-level signaling in GDDR6x and GDDR 7 to relax on-chip frequency requirements has only heightened the need for more rigorous co-design of transceiver\, package and system characteristi cs. And\, of course\, the integration of silicon interposers to support Hi gh Bandwidth Memory (HBM) has driven a paradigm shift in memory interface design. With all of these adaptations\, and many others not captured here\ , the splintering DRAM family continues to push the boundaries of single-e nded signaling into the future.&nbsp\;This presentation briefly explores w hat has driven the diversification in DRAM signaling schemes over the deca des\, will discuss the motivation behind present embodiments\, and will pr oject into the future to where the DRAM interface is likely headed (e.g.\, features and functions necessary for continued energy-efficient bandwidth scaling).</p>\n</div>\n<div>&nbsp\;</div>\n<div>BIOGRAPHY</div>\n<div>\n< p class="MsoNormal">Tim Hollis received the Ph.D. degree in electrical eng ineering from Brigham Young University\, Provo\, UT\, USA\, in 2007. &nbsp \;In 2006\, he joined the Advanced Architecture Group at Micron Technology in Boise\, Idaho\, USA where he contributed to several pathfinding activi ties including the first-generation Hybrid Memory Cube. From 2012 to 2014\ , he worked as a chipset architect at Qualcomm in San Diego\, CA\, USA. He returned to Micron in 2014\, where he currently leads the Interface Pathf inding Group as a Micron Fellow. He has published 18 articles in journals\ , conference proceedings\, and technical magazines\, and holds 274 issued U.S. and international patents. Dr. Hollis served as a member of the IEEE Workshop on Microelectronics and Electron Devices Organizing Committee fro m 2010-2024\, including the General Chair in 2013. He has served on other IEEE conference committees as well as DesignCon&rsquo\;s Technical Program Committee from 2013 to 2015. From 2017 to 2020 he served as the Technolog y Editor for the IEEE Solid-State Circuits Magazine and as a Guest Editor for memory- and interface-related special issues in 2016 and 2019\, respec tively.</p>\n</div> END:VEVENT END:VCALENDAR