BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:Europe/Warsaw BEGIN:DAYLIGHT DTSTART:20260329T030000 TZOFFSETFROM:+0100 TZOFFSETTO:+0200 RRULE:FREQ=YEARLY;BYDAY=-1SU;BYMONTH=3 TZNAME:CEST END:DAYLIGHT BEGIN:STANDARD DTSTART:20251026T020000 TZOFFSETFROM:+0200 TZOFFSETTO:+0100 RRULE:FREQ=YEARLY;BYDAY=-1SU;BYMONTH=10 TZNAME:CET END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20251209T101818Z UID:387E3B60-A612-4837-9F94-62AF40C6F310 DTSTART;TZID=Europe/Warsaw:20251208T144500 DTEND;TZID=Europe/Warsaw:20251208T164500 DESCRIPTION:Hybrid Event: Monday\, 8th December 2025 14:45 - 16:45\, AGH Un iversity\, building B-1 121 lecture hall.\n\nDirect Frequency Modulation o f ADPLLs\n\nBogdan Staszewski (UCD Dublin)\n\nThe past two decades has see n proliferation of all-digital phase-locked loops (ADPLL) for RF and high- performance frequency synthesis due to their clear benefits of flexibility \, reconfigurability\, transfer function precision\, settling speed\, freq uency modulation capability\, and amenability to integration with digital baseband and application processors. When implemented in nanoscale CMOS\, the ADPLL also exhibits advantages of better performance\, lower power con sumption\, lower area and cost over the traditional analog-intensive charg e-pump PLL. In a typical ADPLL\, a traditional VCO got directly replaced b y a digitally controlled oscillator (DCO) for generating an output variabl e clock\, a traditional phase/frequency detector and a charge pump got rep laced by a time-to-digital converter (TDC) for detecting phase departures of the variable clock versus the frequency reference (FREF) clock\, and an analog loop RC filter got replaced with a digital loop filter. The conver sion gains of the DCO and TDC circuits are readily estimated and compensat ed using “free” but powerful digital logic.\n\nThe first talk covered the fundamentals of ADPLL. The second talk covered the loop response of AD PLL. This\, third talk will cover the gear-shifting and direct frequency m odulation capabilities of ADPLL.\n\nDigitally Assisted Gain-Boosted Charge Sharing Locking for Next-Generation mm-Wave PLLs\n\nTeerachot Siriburanon (UCD Dublin)\nAbstract: Conventional charge-sharing locking (CSL) PLLs ac hieve low jitter but rely on large charge-sharing capacitors that periodic ally load the LC-tank\, leading to high reference spurs. Our prior ping-po ng (PP) CSL architecture alleviated this by using complementary charge-sha ring paths and calibration loops to strengthen injection and improve spur behavior. Yet at mm-wave frequencies\, CSL remains constrained by the trad eoff between injection strength and LC-tank loading\, which limits tuning range and restricts operation at higher frequencies. This talk introduces a digitally-assisted gain-boosting (GB) CSL PLL that overcomes this constr aint by sensing the CSL charge residue\, digitally amplifying it\, and rei njecting it through a small\, minimally loading capacitor. This digitally assisted method preserves strong phase correction and high spectral purity with low spurious tones. Together\, these advances demonstrate CSL as a h igh performance solution for next-generation mm-wave frequency synthesis.\ n\nRoom: 121\, Bldg: B1\, AGH University\, Krakow\, Malopolskie\, Poland\, 30-059\, Virtual: https://events.vtools.ieee.org/m/519153 LOCATION:Room: 121\, Bldg: B1\, AGH University\, Krakow\, Malopolskie\, Pol and\, 30-059\, Virtual: https://events.vtools.ieee.org/m/519153 ORGANIZER:kasinski@agh.edu.pl SEQUENCE:13 SUMMARY:Advanced topics of Phase-Locked Loops (Bogdan Staszewski\, Teeracho t Siriburanon) URL;VALUE=URI:https://events.vtools.ieee.org/m/519153 X-ALT-DESC:Description: <br /><p>Hybrid Event: Monday\, 8th December 2025 1 4:45 - 16:45\, AGH University\, building B-1 121 lecture hall.</p>\n<p>&nb sp\;</p>\n<p><strong><span data-olk-copy-source="MessageBody">Direct Frequ ency Modulation of ADPLLs</span></strong></p>\n<p><span data-olk-copy-sour ce="MessageBody">Bogdan Staszewski (UCD Dublin)</span></p>\n<p>The past tw o decades has seen proliferation of all-digital phase-locked loops (ADPLL) for RF and high-performance frequency synthesis due to their clear benefi ts of flexibility\, reconfigurability\, transfer function precision\, sett ling speed\, frequency modulation capability\, and amenability to integrat ion with digital baseband and application processors. When implemented in nanoscale CMOS\, the ADPLL also exhibits advantages of better performance\ , lower power consumption\, lower area and cost over the traditional analo g-intensive charge-pump PLL. In a typical ADPLL\, a traditional VCO got di rectly replaced by a digitally controlled oscillator (DCO) for generating an output variable clock\, a traditional phase/frequency detector and a ch arge pump got replaced by a time-to-digital converter (TDC) for detecting phase departures of the variable clock versus the frequency reference (FRE F) clock\, and an analog loop RC filter got replaced with a digital loop f ilter. The conversion gains of the DCO and TDC circuits are readily estima ted and compensated using &ldquo\;free&rdquo\; but powerful digital logic. </p>\n<p>The first talk covered the fundamentals of ADPLL. The second talk covered the loop response of ADPLL. <span style="text-decoration: underli ne\;">This\, third talk will cover the gear-shifting and direct frequency modulation capabilities of ADPLL.</span></p>\n<p>&nbsp\;</p>\n<p><strong>D igitally Assisted Gain-Boosted Charge Sharing Locking for Next-Generation mm-Wave PLLs</strong></p>\n<p>Teerachot Siriburanon (UCD Dublin)<br>Abstra ct: Conventional charge-sharing locking (CSL) PLLs achieve low jitter but rely on large charge-sharing capacitors that periodically load the LC-tank \, leading to high reference spurs. Our prior ping-pong (PP) CSL architect ure alleviated this by using complementary charge-sharing paths and calibr ation loops to strengthen injection and improve spur behavior. Yet at mm-w ave frequencies\, CSL remains constrained by the tradeoff between injectio n strength and LC-tank loading\, which limits tuning range and restricts o peration at higher frequencies. This talk introduces a digitally-assisted gain-boosting (GB) CSL PLL that overcomes this constraint by sensing the C SL charge residue\, digitally amplifying it\, and reinjecting it through a small\, minimally loading capacitor. This digitally assisted method prese rves strong phase correction and high spectral purity with low spurious to nes. Together\, these advances demonstrate CSL as a high performance solut ion for next-generation mm-wave frequency synthesis.</p>\n<p>&nbsp\;</p> END:VEVENT END:VCALENDAR