BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:America/Los_Angeles BEGIN:DAYLIGHT DTSTART:20260308T030000 TZOFFSETFROM:-0800 TZOFFSETTO:-0700 RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3 TZNAME:PDT END:DAYLIGHT BEGIN:STANDARD DTSTART:20251102T010000 TZOFFSETFROM:-0700 TZOFFSETTO:-0800 RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11 TZNAME:PST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20251206T173025Z UID:BDD349F4-8EFC-4E2A-9213-DF11D24F25C0 DTSTART;TZID=America/Los_Angeles:20251204T171500 DTEND;TZID=America/Los_Angeles:20251204T183000 DESCRIPTION:ABSTRACT\n\nDRAM standards have evolved tremendously over the l ast two-and-a-half decades\, leading to diversification not only in the ar chitecture of the memory array but also in that of the off-chip interface. Application-specific signaling channels have influenced the transceiver d esign nearly as much as system power and bandwidth requirements have. The influence of the multidrop server channel\, along with a broad range of ta rget environments\, has led the DDR branch of JEDEC DRAMs to incorporate m ulti tap Decision Feedback Equalization to maximize flexibility\, while sh rinking supply voltages to facilitate energy reduction have led Low-Power DDR (LPDDR) to completely rethink the output driver structure. In parallel \, Graphics DDR (GDDR) has reached speeds requiring nearly equal care of t he external channel and the chip itself. The adoption of multi-level signa ling in GDDR6x and GDDR7 to relax on-chip frequency requirements has only heightened the need for more rigorous co-design of transceiver\, package a nd system characteristics. And\, of course\, the integration of silicon in terposers to support High Bandwidth Memory (HBM) has driven a paradigm shi ft in memory interface design. With all of these adaptations\, and many ot hers not captured here\, the splintering DRAM family continues to push the boundaries of single-ended signaling into the future. This presentation b riefly explores what has driven the diversification in DRAM signaling sche mes over the decades\, will discuss the motivation behind present embodime nts\, and will project into the future to where the DRAM interface is like ly headed (e.g.\, features and functions necessary for continued energy-ef ficient bandwidth scaling).\n\nBldg: Qualcomm Q Auditorium\, SAN DIEGO\, C alifornia\, United States\, 92130 LOCATION:Bldg: Qualcomm Q Auditorium\, SAN DIEGO\, California\, United Stat es\, 92130 ORGANIZER:jfshi@ieee.org SEQUENCE:6 SUMMARY:Memory Interfaces – Past\, Present and Future URL;VALUE=URI:https://events.vtools.ieee.org/m/520387 X-ALT-DESC:Description: <br /><div>ABSTRACT</div>\n<div>\n<p class="MsoNorm al">DRAM standards have evolved tremendously over the last two-and-a-half decades\, leading to diversification not only in the architecture of the m emory array but also in that of the off-chip interface. Application-specif ic signaling channels have influenced the transceiver design nearly as muc h as system power and bandwidth requirements have. The influence of the mu ltidrop server channel\, along with a broad range of target environments\, has led the DDR branch of JEDEC DRAMs to incorporate multi tap Decision F eedback Equalization to maximize flexibility\, while shrinking supply volt ages to facilitate energy reduction have led Low-Power DDR (LPDDR) to comp letely rethink the output driver structure. In parallel\, Graphics DDR (GD DR) has reached speeds requiring nearly equal care of the external channel and the chip itself. The adoption of multi-level signaling in GDDR6x and GDDR7 to relax on-chip frequency requirements has only heightened the need for more rigorous co-design of transceiver\, package and system character istics. And\, of course\, the integration of silicon interposers to suppor t High Bandwidth Memory (HBM) has driven a paradigm shift in memory interf ace design. With all of these adaptations\, and many others not captured h ere\, the splintering DRAM family continues to push the boundaries of sing le-ended signaling into the future. This presentation briefly explores wha t has driven the diversification in DRAM signaling schemes over the decade s\, will discuss the motivation behind present embodiments\, and will proj ect into the future to where the DRAM interface is likely headed (e.g.\, f eatures and functions necessary for continued energy-efficient bandwidth s caling).</p>\n</div> END:VEVENT END:VCALENDAR