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TZID:Asia/Shanghai
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DTSTART:19910915T010000
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TZOFFSETTO:+0800
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BEGIN:VEVENT
DTSTAMP:20251218T174021Z
UID:27DC77BB-619D-428B-BFAB-305DE3CED0A9
DTSTART;TZID=Asia/Shanghai:20251212T013000
DTEND;TZID=Asia/Shanghai:20251212T013200
DESCRIPTION:We are pleased to announce that the &quot;2025 Mini-Power IC Worksho
 p Shenzhen\,&quot; jointly organized by the Department of Electronic and Electr
 ical Engineering\, College of Engineering\, Southern University of Science
  and Technology (SUSTech)\, IEEE Circuits and Systems Society - Shenzhen C
 hapter\, and IEEE Circuits and Systems Society - Macau Chapter\, and co-or
 ganized by the University of Macau (UM) – He Tao Integrated Circuit Rese
 arch Institute\, will be held on Friday\, Dec. 12\, 2025\, in Room 813\, S
 outh Building\, College of Engineering\, Southern University of Science an
 d Technology.\n\nThis workshop brings together leading universities\, rese
 arch institutions\, and enterprises in the field of power ICs. The event w
 ill focus on key topics in power electronics\, including integrated power 
 electronic circuits and system design\, wide-bandgap semiconductor devices
  and system integration\, as well as core technologies and cutting-edge ap
 plications such as IoT\, energy harvesting\, on-board power supplies\, and
  advanced magnetic design. Over 10 technical sessions will be conducted to
  facilitate in-depth discussions.\n\nCo-sponsored by: IEEE CAS Society\n\n
 Speaker(s): Junrui Liang\, Yan Lu\, Wing-Hung Ki\n\nAgenda: \n2025 Mini Po
 wer IC Workshop Shenzhen\nTime: 2025-12-12 (Friday)\nLocation: South Tower
  813 Lecture Hall\, College of Engineering\, Southern University of Scienc
 e and Technology (SUSTech)\nOpening\n\n8:30-9:00\nChen Mingwei\, Chair Pro
 fessor\nDean\, College of Engineering\, SUSTech\n\nTechnical Workshop (Mor
 ning 1: Host: Jiang Junmin)\n9:00-9:40\nWing-Hung Ki\nProfessor，HKUST\nM
 y Ground-Clearing Attempts of Power Management Integrated Circuit Research
 \n\n9:40-10:05\nDavid Zhou\nChief Scientist of GaN，\nShenzhen Pinghu Lab
 oratory\nResearch Progress on 8-inch Power GaN and Integration Technology 
 for the AI Era\n\n10:05-10:30\nCheng Lin\nProfessor，USTC\nComputing Chip
  Power Supply Technology: Architectural Evolution and Integrated Voltage R
 egulator (IVR) Design\n\n10:30-10:45\nTea Break\n\nTechnical Workshop (Mor
 ning 2: Host: Jiang Yang)\n\n10:45-11:10\nMing Xin\nProfessor，UESTC\nDev
 elopment Trends and Technical Challenges of High-Frequency Driver ICs for 
 Low-Voltage GaN\n\n11:10-11:35\nGao Ziyang\nSenior Director，Hong Kong Mi
 croelectronics Research Institute\nAn Active EMI Filter Integrated Circuit
  Using Negative Capacitance Concept for Common Mode Noise Attenuation\n\n1
 1:35-12:00\nZhang Weijia\nAssistant Professor，HKUST\nDynamic Gate Driver
  for GaN Power Devices\n\n12:00-13:30\nLunch Break\n\nTechnical Workshop (
 Afternoon 1: Host: Gao Yuan)\n\n13:35-14:00\nWang Haoyu\nProfessor，Shang
 haiTech University\nBandwidth Ultra-Fast Point-of-Load Power Supply for AI
  Data Centers\n\n14:00-14:25\nWang Ping\nAssistant Professor，HKUST\nA Gr
 anular Hybrid Switched-Capacitor/-Magnetics Approach for High-Current AI P
 rocessors\n\n14:25-14:50\nZeng Wenliang\nAssistant Professor，U. of Macau
 \nChiplet-LEGO: Delivering Multiple Voltage Rails to Chiplets with Chiplet
  VRMs\n\nPh.D. Reports and Poster Session\n\n14:50-15:20\nPh.D. Reports\nL
 iu Zeguo\, Wang Shiyuan\, Liu Gang\, Mu Xuchu\, Cui Kai\, Chu Peng\, Shi J
 iahao\, Liu Yingming\, Wu Han\n\n15:20-15:50\nPh.D. Poster Session\nBest P
 oster Award Selection\n\nIEEE CASS Distinguish Lecture Special Session（H
 ost: Jiang Junmin)\n\n15:50-16:15\nLiang Junrui\nAssociate Professor，Sha
 nghaiTech University\nA Deep Fusion of Power Electronics and Kinetic Energ
 y Harvesters Toward Motion-powered IoT Systems\n\n16:15-16:40\nLu Yan\nPro
 fessor，Tsinghua University\n2.5D/3D Vertical Power Delivery for Chiplet 
 Systems\n\nSouth Tower 813 Lecture Hall\, College of Engineering\, Souther
 n University of Science and Technology (SUSTech)\, Shenzhen\, Guangdong\, 
 China
LOCATION:South Tower 813 Lecture Hall\, College of Engineering\, Southern U
 niversity of Science and Technology (SUSTech)\, Shenzhen\, Guangdong\, Chi
 na
ORGANIZER:jiangjm@sustech.edu.cn
SEQUENCE:14
SUMMARY:2025 Mini-Power IC Workshop Shenzhen
URL;VALUE=URI:https://events.vtools.ieee.org/m/520389
X-ALT-DESC:Description: &lt;br /&gt;&lt;p class=&quot;MsoNormal&quot; style=&quot;margin-bottom: 6.
 0pt\; mso-para-margin-bottom: .5gd\; text-align: justify\; text-justify: i
 nter-ideograph\; background: white\;&quot;&gt;&lt;span lang=&quot;EN-US&quot; style=&quot;font-size:
  14.0pt\; font-family: &#39;Calibri&#39;\,sans-serif\; mso-fareast-font-family: &#39;
 等线 Light&#39;\; mso-fareast-theme-font: major-latin\; color: #333333\;&quot;&gt;We
  are pleased to announce that the &quot;2025 Mini-Power IC Workshop Shenzhen\,&quot;
  jointly organized by the Department of Electronic and Electrical Engineer
 ing\, College of Engineering\, Southern University of Science and Technolo
 gy (SUSTech)\, IEEE Circuits and Systems Society - Shenzhen Chapter\, and 
 IEEE Circuits and Systems Society - Macau Chapter\, and co-organized by th
 e University of Macau (UM) &amp;ndash\; He Tao Integrated Circuit Research Ins
 titute\, will be held on &lt;strong&gt;Friday\, Dec. 12\, 2025&lt;/strong&gt;\, in &lt;st
 rong&gt;Room 813\, South Building\, College of Engineering\, Southern Univers
 ity of Science and Technology&lt;/strong&gt;.&lt;/span&gt;&lt;/p&gt;\n&lt;p class=&quot;MsoNormal&quot; s
 tyle=&quot;margin-bottom: 6.0pt\; mso-para-margin-bottom: .5gd\; text-align: ju
 stify\; text-justify: inter-ideograph\; background: white\;&quot;&gt;&lt;span lang=&quot;E
 N-US&quot; style=&quot;font-size: 14.0pt\; font-family: &#39;Calibri&#39;\,sans-serif\; mso-
 fareast-font-family: &#39;等线 Light&#39;\; mso-fareast-theme-font: major-latin\
 ; color: #333333\;&quot;&gt;This workshop brings together leading universities\, r
 esearch institutions\, and enterprises in the field of power ICs. The even
 t will focus on key topics in power electronics\, including integrated pow
 er electronic circuits and system design\, wide-bandgap semiconductor devi
 ces and system integration\, as well as core technologies and cutting-edge
  applications such as IoT\, energy harvesting\, on-board power supplies\, 
 and advanced magnetic design. Over 10 technical sessions will be conducted
  to facilitate in-depth discussions.&lt;/span&gt;&lt;/p&gt;&lt;br /&gt;&lt;br /&gt;Agenda: &lt;br /&gt;&lt;
 p&gt;2025 Mini Power IC Workshop Shenzhen&lt;br&gt;Time: 2025-12-12 (Friday)&lt;br&gt;Loc
 ation: South Tower 813 Lecture Hall\, College of Engineering\, Southern Un
 iversity of Science and Technology (SUSTech)&lt;br&gt;Opening&lt;/p&gt;\n&lt;p&gt;8:30-9:00&lt;
 br&gt;Chen Mingwei\, Chair Professor&lt;br&gt;Dean\, College of Engineering\, SUSTe
 ch&lt;/p&gt;\n&lt;p&gt;Technical Workshop (Morning 1: Host: Jiang Junmin)&lt;br&gt;9:00-9:40
 &lt;br&gt;Wing-Hung Ki&lt;br&gt;Professor，HKUST&lt;br&gt;My Ground-Clearing Attempts of Po
 wer Management Integrated Circuit Research&lt;/p&gt;\n&lt;p&gt;9:40-10:05&lt;br&gt;David Zho
 u&lt;br&gt;Chief Scientist of GaN，&lt;br&gt;Shenzhen Pinghu Laboratory&lt;br&gt;Research P
 rogress on 8-inch Power GaN and Integration Technology for the AI Era&lt;/p&gt;\
 n&lt;p&gt;10:05-10:30&lt;br&gt;Cheng Lin&lt;br&gt;Professor，USTC&lt;br&gt;Computing Chip Power S
 upply Technology: Architectural Evolution and Integrated Voltage Regulator
  (IVR) Design&lt;/p&gt;\n&lt;p&gt;10:30-10:45&lt;br&gt;Tea Break&lt;/p&gt;\n&lt;p&gt;Technical Workshop 
 (Morning 2: Host: Jiang Yang)&lt;/p&gt;\n&lt;p&gt;10:45-11:10&lt;br&gt;Ming Xin&lt;br&gt;Professor
 ，UESTC&lt;br&gt;Development Trends and Technical Challenges of High-Frequency 
 Driver ICs for Low-Voltage GaN&lt;/p&gt;\n&lt;p&gt;11:10-11:35&lt;br&gt;Gao Ziyang&lt;br&gt;Senior
  Director，Hong Kong Microelectronics Research Institute&lt;br&gt;An Active EMI
  Filter Integrated Circuit Using Negative Capacitance Concept for Common M
 ode Noise Attenuation&lt;/p&gt;\n&lt;p&gt;11:35-12:00&lt;br&gt;Zhang Weijia&lt;br&gt;Assistant Pro
 fessor，HKUST&lt;br&gt;Dynamic Gate Driver for GaN Power Devices&lt;/p&gt;\n&lt;p&gt;12:00-
 13:30&lt;br&gt;Lunch Break&lt;/p&gt;\n&lt;p&gt;Technical Workshop (Afternoon 1: Host: Gao Yu
 an)&lt;/p&gt;\n&lt;p&gt;13:35-14:00&lt;br&gt;Wang Haoyu&lt;br&gt;Professor，ShanghaiTech Universi
 ty&lt;br&gt;Bandwidth Ultra-Fast Point-of-Load Power Supply for AI Data Centers&lt;
 /p&gt;\n&lt;p&gt;14:00-14:25&lt;br&gt;Wang Ping&lt;br&gt;Assistant Professor，HKUST&lt;br&gt;A Granu
 lar Hybrid Switched-Capacitor/-Magnetics Approach for High-Current AI Proc
 essors&lt;/p&gt;\n&lt;p&gt;14:25-14:50&lt;br&gt;Zeng Wenliang&lt;br&gt;Assistant Professor，U. of
  Macau&lt;br&gt;Chiplet-LEGO: Delivering Multiple Voltage Rails to Chiplets with
  Chiplet VRMs&lt;/p&gt;\n&lt;p&gt;Ph.D. Reports and Poster Session&lt;/p&gt;\n&lt;p&gt;14:50-15:20
 &lt;br&gt;Ph.D. Reports&lt;br&gt;Liu Zeguo\, Wang Shiyuan\, Liu Gang\, Mu Xuchu\, Cui 
 Kai\, Chu Peng\, Shi Jiahao\, Liu Yingming\, Wu Han&lt;/p&gt;\n&lt;p&gt;15:20-15:50&lt;br
 &gt;Ph.D. Poster Session&lt;br&gt;Best Poster Award Selection&lt;/p&gt;\n&lt;p&gt;IEEE CASS Dis
 tinguish Lecture Special Session（Host: Jiang Junmin)&lt;/p&gt;\n&lt;p&gt;15:50-16:15
 &lt;br&gt;Liang Junrui&lt;br&gt;Associate Professor，ShanghaiTech University&lt;br&gt;A Dee
 p Fusion of Power Electronics and Kinetic Energy Harvesters Toward Motion-
 powered IoT Systems&lt;/p&gt;\n&lt;p&gt;16:15-16:40&lt;br&gt;Lu Yan&lt;br&gt;Professor，Tsinghua 
 University&lt;br&gt;2.5D/3D Vertical Power Delivery for Chiplet Systems&lt;/p&gt;
END:VEVENT
END:VCALENDAR