BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:Asia/Taipei BEGIN:STANDARD DTSTART:19790930T230000 TZOFFSETFROM:+0900 TZOFFSETTO:+0800 TZNAME:CST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20260122T082120Z UID:9CD38135-99F5-4DA3-BB71-5B5E8B2CA2D4 DTSTART;TZID=Asia/Taipei:20251211T090000 DTEND;TZID=Asia/Taipei:20251211T120100 DESCRIPTION:研討會主題：RFSoC 和 PYNQ 的實際應用：\n\n從 5G 到量子及未來\n\n由羅伯特·史都華、安德魯·麥克萊倫、 馬裡烏斯·西奧丘利斯和路易絲·克羅克特開發和呈現\n\n 英國蘇格蘭格拉斯哥斯特拉斯克萊德大學。\n\nDate\, time a nd venue: 09:00 – 12:00\, Thursday 11th December\, ED 417B\n\nAgenda: \ nAbstract\n\nThis workshop introduces a modern\, application-driven approa ch to building high-performance radio systems using AMD’s Radio Frequenc y System-on-Chip (RFSoC) technology. RFSoC devices combine FPGA fabric\, a pplication processor cores\, and high-speed Radio Frequency (RF) data conv erters (DACs and ADCs)\, operating at multiple Gigasamples per second (Gsp s) in a single chip\, enabling high bandwidth and real-time operation dire ctly at the edge.\n\nThis workshop focuses on how RFSoC-specific features can be used to build advanced wireless\, sensing\, and instrumentation\, f or applications like 5G communications and quantum. Through demonstrations and practical examples\, we explore high-speed data capture techniques\, FPGA-accelerated signal processing\, and emerging workflows for deploying edge AI models and custom AI accelerators on RFSoC hardware. The workshop showcases end-to-end design strategies supported by the RFSoC-PYNQ framewo rk\, enabling researchers to rapidly prototype and evaluate complex RF sys tems.\n\nHsinchu\, T'ai-wan\, Taiwan LOCATION:Hsinchu\, T'ai-wan\, Taiwan ORGANIZER:ie3taipeisection@gmail.com SEQUENCE:7 SUMMARY:RFSoC & PYNQ in Action: From 5G to Quantum and Beyond URL;VALUE=URI:https://events.vtools.ieee.org/m/520914 X-ALT-DESC:Description: <br /><p class="MsoNormal"><span lang="EN-GB" style ="font-size: 16.0pt\; mso-bidi-font-size: 11.0pt\; line-height: 107%\;"><s pan dir="auto" style="vertical-align: inherit\;"><span dir="auto" style="v ertical-align: inherit\;">研討會主題：</span><strong style="mso-bidi -font-weight: normal\;"><span dir="auto" style="vertical-align: inherit\;" >RFSoC 和 PYNQ 的實際應用：</span></strong></span><strong style="ms o-bidi-font-weight: normal\;"> <span style="mso-tab-count: 1\;">&nbsp\;&nb sp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\; </span></strong></span></p>\n<p class="Ms oNormal" style="margin-left: 108.0pt\; text-indent: 36.0pt\;"><strong styl e="mso-bidi-font-weight: normal\;"><span lang="EN-GB" style="font-size: 16 .0pt\; mso-bidi-font-size: 11.0pt\; line-height: 107%\;"><span dir="auto" style="vertical-align: inherit\;"><span dir="auto" style="vertical-align: inherit\;">從 5G 到量子及未來</span></span></span></strong></p>\n<p class="MsoNormal"><span lang="EN-GB"><span dir="auto" style="vertical-ali gn: inherit\;"><span dir="auto" style="vertical-align: inherit\;">由</spa n><strong style="mso-bidi-font-weight: normal\;"><span dir="auto" style="v ertical-align: inherit\;">羅伯特&middot\;史都華、安德魯&middot\; 麥克萊倫、馬裡烏斯&middot\;西奧丘利斯和路易絲&middot\; 克羅克特開發和呈現</span></strong></span><span style="mso-tab-cou nt: 1\;">&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\; </span></span></p>\n<p class="MsoNormal"><strong style="mso-bidi-font-weight: normal\;"><span la ng="EN-GB"><span style="mso-tab-count: 4\;">&nbsp\;&nbsp\;&nbsp\;&nbsp\;&n bsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\ ;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nb sp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\; &nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbs p\; </span><span dir="auto" style="vertical-align: inherit\;"><span dir="a uto" style="vertical-align: inherit\;">英國蘇格蘭格拉斯哥斯特 拉斯克萊德大學。</span></span></span></strong></p>\n<p class="MsoN ormal"><span lang="EN-GB">Date\, time and venue:<strong style="mso-bidi-fo nt-weight: normal\;"><span style="mso-tab-count: 1\;">&nbsp\;&nbsp\; </spa n><span style="mso-tab-count: 1\;">&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbs p\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\; </span>09:00 &ndash\; 12:00\, Thurs day 1</strong></span><strong style="mso-bidi-font-weight: normal\;"><span lang="EN-GB" style="mso-fareast-language: ZH-TW\;">1</span><sup><span lang ="EN-GB">th</span></sup><span lang="EN-GB"> December\, ED 417B</span></str ong></p><br /><br />Agenda: <br /><p class="MsoNormal"><strong style="mso- bidi-font-weight: normal\;"><span lang="EN-GB" style="font-size: 10.0pt\; mso-bidi-font-size: 11.0pt\; line-height: 107%\; color: #0070c0\;">Abstrac t</span></strong></p>\n<p class="MsoNormal"><span lang="EN-GB" style="font -size: 10.0pt\; mso-bidi-font-size: 11.0pt\; line-height: 107%\;">This wor kshop introduces a modern\, application-driven approach to building high-p erformance radio systems using AMD&rsquo\;s Radio Frequency System-on-Chip (RFSoC) technology. RFSoC devices combine FPGA fabric\, application proce ssor cores\, and high-speed Radio Frequency (RF) data converters (DACs and ADCs)\, operating at multiple Gigasamples per second (Gsps) in a single c hip\, enabling high bandwidth and real-time operation directly at the edge . </span></p>\n<p class="MsoNormal"><span lang="EN-GB" style="font-size: 1 0.0pt\; mso-bidi-font-size: 11.0pt\; line-height: 107%\;">This workshop fo cuses on how RFSoC-specific features can be used to build advanced wireles s\, sensing\, and instrumentation\, for applications like 5G communication s and quantum. Through demonstrations and practical examples\, we explore high-speed data capture techniques\, FPGA-accelerated signal processing\, and emerging workflows for deploying edge AI models and custom AI accelera tors on RFSoC hardware. The workshop showcases end-to-end design strategie s supported by the RFSoC-PYNQ framework\, enabling researchers to rapidly prototype and evaluate complex RF systems.</span></p>\n<p>&nbsp\;</p> END:VEVENT END:VCALENDAR