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VERSION:2.0
PRODID:IEEE vTools.Events//EN
CALSCALE:GREGORIAN
BEGIN:VTIMEZONE
TZID:Asia/Kolkata
BEGIN:STANDARD
DTSTART:19451014T230000
TZOFFSETFROM:+0630
TZOFFSETTO:+0530
TZNAME:IST
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BEGIN:VEVENT
DTSTAMP:20260109T101235Z
UID:D79E1910-9467-404F-89A8-7D622F23305A
DTSTART;TZID=Asia/Kolkata:20260106T150000
DTEND;TZID=Asia/Kolkata:20260106T163000
DESCRIPTION:Data conversion\, storing in volatile memories\, transmission\,
  and computation impose high energy consumption\, latency\, and a memory b
 ottleneck. To achieve energy efficiency new low power nanoscale devices ar
 e required for the integration of sensing and in-memory computation to eff
 iciently enable Artificial Intelligence (AI) on resource-limited systems. 
 Resistive random-access memory (RRAM) devices are currently being investig
 ated for possible implementation of artificial intelligence hardware throu
 gh in-memory computing. The electrical performance in these devices depend
 s on the dielectric deposition process\, precise selection of deposition p
 arameters\, pre-deposition surface treatments and subsequent thermal budge
 t. The talk will discuss the RRAM devices with hydrogen plasma treated hig
 h-k dielectric stacks that have shown low power switching and good conduct
 ance quantization with programing pulsed operation that qualify them to be
  used for in-memory computing. Engineering the distribution of defects or 
 oxygen vacancies near the top and bottom electrodes has a significant impa
 ct on reducing the switching power and improving the multi-level cell (MLC
 ) characteristics of the device.\n\nSpeaker(s): Durga\, \n\nBldg: Senate H
 all\, IIITDM Kancheepuram\, Vandalur-Kelambakkam Road\, Chennai\, Tamil Na
 du\, India\, 600127
LOCATION:Bldg: Senate Hall\, IIITDM Kancheepuram\, Vandalur-Kelambakkam Roa
 d\, Chennai\, Tamil Nadu\, India\, 600127
ORGANIZER:kppradhan@iiitdm.ac.in
SEQUENCE:29
SUMMARY:Engineering the Power Efficiency of RRAM Devices for In-Memory Comp
 uting
URL;VALUE=URI:https://events.vtools.ieee.org/m/523559
X-ALT-DESC:Description: <br /><p class="MsoNormal" style="text-align: justi
 fy\;"><span lang="EN-US" style="font-family: 'Times New Roman'\,serif\; ms
 o-fareast-language: KO\;">Data conversion\, storing in volatile memories\,
  transmission\, and computation impose high energy consumption\, latency\,
  and a memory bottleneck. To achieve energy efficiency new low power nanos
 cale devices are required for the integration of sensing and in-memory com
 putation to efficiently enable Artificial Intelligence (AI) on resource-li
 mited systems. Resistive random-access memory (RRAM) devices are currently
  being investigated for possible implementation of artificial intelligence
  hardware through in-memory computing. The electrical performance in these
  devices depends on the dielectric deposition process\, precise selection 
 of deposition parameters\, pre-deposition surface treatments and subsequen
 t thermal budget. The talk will discuss the RRAM devices with hydrogen pla
 sma treated high-k dielectric stacks that have shown low power switching a
 nd good conductance quantization with programing pulsed operation that qua
 lify them to be used for in-memory computing. Engineering the distribution
  of defects or oxygen vacancies near the top and bottom electrodes has a s
 ignificant impact on reducing the switching power and improving the multi-
 level cell (MLC) characteristics of the device.</span></p>
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END:VCALENDAR