BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:Asia/Kolkata BEGIN:STANDARD DTSTART:19451014T230000 TZOFFSETFROM:+0630 TZOFFSETTO:+0530 TZNAME:IST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20251230T082023Z UID:333258B2-3276-4451-BDAA-1500B4161B7A DTSTART;TZID=Asia/Kolkata:20250525T103000 DTEND;TZID=Asia/Kolkata:20250525T160000 DESCRIPTION:The “Verilogic Showdown” was a dynamic and intellectually s timulating competition conducted on 24th May 2025 at the Department of Ele ctronics and Instrumentation\, Bangalore Institute of Technology. The even t tested participants' skills in writing efficient Verilog code for real-t ime hardware problems. Each team’s group lead picked a chit containing a Verilog problem statement. Participants were required to implement the gi ven\ntask within a fixed time frame using Verilog.\n\nProblem Statements\n 1. Stepper Motor Control – Rotate 4 steps clockwise and 8 steps anticloc kwise.\n2. Sine Wave Generation – Write a Verilog program to generate a sine wave.\n3. Speed-Controlled Stepper Motor – Rotate at different spee ds in opposite directions.\n4. Ramp Wave Generation – Generate a ramp wa ve using Verilog.\n5. MOD-8 Counter – Synchronous counter with control s ignal to count up/down.\n6. SIPO Register Implementation – Serial-In Par allel-Out register design in FPGA.\n7. Telephone Booth Controller – Coin -based FSM design with test bench and synthesis.\n8. Binary to Gray Code C onverter – Using 1-bit full adder/subtractor.\n9. LED Blinking Pattern – 4 onboard LEDs blinking to simulate clockwise and anticlockwise direct ion.\n10. Vending Machine FSM – Dispense product on receiving 5 rupees f rom 1/2 rupee coins.\n\nJudging Criteria\nThe submissions were evaluated b ased on the following criteria:\n\n• Correctness of Logic\n\n• Efficie ncy of the Code\n\n• Simulation Output Accuracy\n\n• FSM Implementatio n (if applicable)\n\n• Bonus Points for Optimization\n\nBldg: Main build ing\, Bangalore Institute Of Technology\, Department Of Electronics Engg ( VDT)\, Bangalore\, Karnataka\, India\, 560004 LOCATION:Bldg: Main building\, Bangalore Institute Of Technology\, Departme nt Of Electronics Engg (VDT)\, Bangalore\, Karnataka\, India\, 560004 ORGANIZER:jalajas@ieee.org SEQUENCE:8 SUMMARY: IEEE Verilog Coding Competition URL;VALUE=URI:https://events.vtools.ieee.org/m/528019 X-ALT-DESC:Description: <br /><p>The &ldquo\;Verilogic Showdown&rdquo\; was a dynamic and intellectually stimulating competition conducted on 24th Ma y 2025 at the Department of Electronics and Instrumentation\, Bangalore In stitute of Technology. The event tested participants' skills in writing ef ficient Verilog code for real-time hardware problems. Each team&rsquo\;s g roup lead picked a chit containing a Verilog problem statement. Participan ts were required to implement the given&nbsp\;<br>task within a fixed time frame using Verilog.</p>\n<p>Problem Statements&nbsp\;<br>&nbsp\;1. Stepp er Motor Control &ndash\; Rotate 4 steps clockwise and 8 steps anticlockwi se.&nbsp\;<br>&nbsp\;2. Sine Wave Generation &ndash\; Write a Verilog prog ram to generate a sine wave.&nbsp\;<br>&nbsp\;3. Speed-Controlled Stepper Motor &ndash\; Rotate at different speeds in opposite directions.&nbsp\;<b r>&nbsp\;4. Ramp Wave Generation &ndash\; Generate a ramp wave using Veril og.&nbsp\;<br>&nbsp\;5. MOD-8 Counter &ndash\; Synchronous counter with co ntrol signal to count up/down.&nbsp\;<br>&nbsp\;6. SIPO Register Implement ation &ndash\; Serial-In Parallel-Out register design in FPGA.&nbsp\;<br>& nbsp\;7. Telephone Booth Controller &ndash\; Coin-based FSM design with te st bench and synthesis.&nbsp\;<br>&nbsp\;8. Binary to Gray Code Converter &ndash\; Using 1-bit full adder/subtractor.&nbsp\;<br>&nbsp\;9. LED Blinki ng Pattern &ndash\; 4 onboard LEDs blinking to simulate clockwise and anti clockwise direction.&nbsp\;<br>&nbsp\;10. Vending Machine FSM &ndash\; Dis pense product on receiving 5 rupees from 1/2 rupee coins.&nbsp\;</p>\n<p>J udging Criteria&nbsp\;<br>The submissions were evaluated based on the foll owing criteria:</p>\n<p>&bull\; Correctness of Logic</p>\n<p>&bull\; Effic iency of the Code</p>\n<p>&bull\; Simulation Output Accuracy</p>\n<p>&bull \; FSM Implementation (if applicable)</p>\n<p>&bull\; Bonus Points for Opt imization</p>\n<p><img src="https://events.vtools.ieee.org/vtools_ui/media /display/49bf3dfd-e714-4ddc-ad8a-3287288f54ef"></p> END:VEVENT END:VCALENDAR