BEGIN:VCALENDAR
VERSION:2.0
PRODID:IEEE vTools.Events//EN
CALSCALE:GREGORIAN
BEGIN:VTIMEZONE
TZID:Asia/Kolkata
BEGIN:STANDARD
DTSTART:19451014T230000
TZOFFSETFROM:+0630
TZOFFSETTO:+0530
TZNAME:IST
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BEGIN:VEVENT
DTSTAMP:20251230T082454Z
UID:8EF57893-8EF6-4645-A52F-DD1D41BB520B
DTSTART;TZID=Asia/Kolkata:20250520T090000
DTEND;TZID=Asia/Kolkata:20250521T170000
DESCRIPTION:IEEE BIT Student Branch conducted a two-day Skill Development W
 orkshop under the IEEE BIT VLSI Chapter on 20th and 21st May 2025. The eve
 nt focused on practical\, industry-relevant skills in FPGA-based design an
 d integration of communication protocols like I2C\, SPI\, and AMBA\, using
  Xilinx Vivado\, a widely-used tool in the VLSI industry.\n\nThe workshop 
 was conducted by Mr. Abhishek Mulugu\, Principal Engineer at Marvell Semic
 onductor\, who is a FPGA design and RTL development specialist with more t
 han fifteen years of experience.\n\nDAY-1:\n\nOn Day-1 of the workshop\, a
 n introductory session on FPGA (Field Programmable Gate Arrays) was conduc
 ted\, focusing on their importance in modern digital design. Participants 
 were introduced to the fundamental concepts of FPGA technology\, including
  types of FPGAs and their applications across fields such as telecommunica
 tions\, consumer electronics\, automotive systems\, and defence. The sessi
 on explained how logic blocks\, interconnects\, and I/O blocks within an F
 PGA work together to create flexible hardware solutions.\n\nDAY-2:\n\nIn t
 his session\, participants learned how to work with IP (Intellectual Prope
 rty) designs in Vivado\, an essential part of modern FPGA development. The
  session began with an overview of how to access and install IP cores with
 in the Vivado environment. Participants were guided on how to navigate the
  IP catalogue\, configure IP cores\, and understand the role of protocols 
 in digital design. Protocols such as I2C\, SPI\, and UART were introduced\
 , explaining their purpose in enabling communication between devices.\n\nB
 ldg: Main building\, Bangalore Institute Of Technology\, Department Of Ele
 ctronics Engg (VDT)\, Bangalore\, Karnataka\, India\, 560004
LOCATION:Bldg: Main building\, Bangalore Institute Of Technology\, Departme
 nt Of Electronics Engg (VDT)\, Bangalore\, Karnataka\, India\, 560004
ORGANIZER:jalajas@ieee.org
SEQUENCE:6
SUMMARY:WORKSHOP ON FPGA AND INDUSTRIAL COMMUNICATION PROTOCOLS
URL;VALUE=URI:https://events.vtools.ieee.org/m/528026
X-ALT-DESC:Description: <br /><p class="MsoNormal"><span lang="EN-US">IEEE 
 BIT Student Branch conducted a two-day Skill Development Workshop under th
 e IEEE BIT VLSI Chapter on 20th and 21st May 2025. The event focused on pr
 actical\, industry-relevant skills in FPGA-based design and integration of
  communication protocols like I2C\, SPI\, and AMBA\, using Xilinx Vivado\,
  a widely-used tool in the VLSI industry.</span></p>\n<p class="MsoNormal"
 >The workshop was conducted by&nbsp\;Mr. Abhishek Mulugu\, Principal Engin
 eer at Marvell Semiconductor\,&nbsp\;who is a FPGA design and RTL developm
 ent specialist with more than fifteen years of experience.</p>\n<p class="
 MsoNormal"><img src="https://events.vtools.ieee.org/vtools_ui/media/displa
 y/f11f059f-6f6d-4e3a-9301-1d8cdcecec4b" width="214" height="208"><img src=
 "https://events.vtools.ieee.org/vtools_ui/media/display/2b190db9-9bb3-44a2
 -ad21-b8b4e5bae9b8" width="174" height="208"><img src="https://events.vtoo
 ls.ieee.org/vtools_ui/media/display/ade7c18c-3d8c-453b-9ffa-add0ea8b0a3b" 
 width="355" height="214"></p>\n<p class="MsoNormal">DAY-1:</p>\n<p class="
 MsoNormal">On Day-1 of the workshop\, an introductory session on FPGA (Fie
 ld Programmable Gate Arrays) was conducted\, focusing on their importance 
 in modern digital design. Participants were introduced to the fundamental 
 concepts of FPGA technology\, including types of FPGAs and their applicati
 ons across fields such as telecommunications\, consumer electronics\, auto
 motive systems\, and defence. The session explained how logic blocks\, int
 erconnects\, and I/O blocks within an FPGA work together to create flexibl
 e hardware solutions.</p>\n<p class="MsoNormal">DAY-2:</p>\n<p class="MsoN
 ormal">In this session\, participants learned how to work with IP (Intelle
 ctual Property) designs in Vivado\, an essential part of modern FPGA devel
 opment. The session began with an overview of how to access and install IP
  cores within the Vivado environment. Participants were guided on how to n
 avigate the IP catalogue\, configure IP cores\, and understand the role of
  protocols in digital design. Protocols such as I2C\, SPI\, and UART were 
 introduced\, explaining their purpose in enabling communication between de
 vices.</p>
END:VEVENT
END:VCALENDAR