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DESCRIPTION:EDS Webinar:\n\nEvolution of metal-oxide-semiconductor device a
 rchitectures and the corresponding requirements on epitaxial growth proces
 ses\n\nAfter a short description of the evolution of metal-oxide-semicondu
 ctor device architectures and the corresponding requirements on epitaxial 
 growth processes\, the material properties of complicated Si/SiGe multi-la
 yer stacks used for complementary field effect transistor (CFET) devices\,
  where gate-all-around nFETs and pFETs are stacked\, will be discussed. Th
 e given layer stack contains two different Ge concentrations and has been 
 grown using conventional process gases. A relatively high growth temperatu
 re is used to obtain acceptable Si and SiGe growth rates. 3D island growth
  has been suppressed for Ge concentrations up to 40%\, despite the rather 
 high growth temperature. Excellent structural and optical material propert
 ies of the Si/SiGe multi-layer stack will be reported\, with up to 3 + 3 S
 i channels in the top and bottom part of the stack\, respectively. The abs
 ence/presence of lattice defects has also been verified by room-temperatur
 e photoluminescence measurements. Photoluminescence measurements at low te
 mperatures are used to study band-to-band luminescence from individual sub
 -layers and to illustrate the optical material quality of the CFET stack.\
 n\nSpeaker(s): Roger Loo\n\nAgenda: \nEDS Webinar:\n\nEvolution of metal-o
 xide-semiconductor device architectures and the corresponding requirements
  on epitaxial growth processes\n\nAbstract:\n\nAfter a short description o
 f the evolution of metal-oxide-semiconductor device architectures and the 
 corresponding requirements on epitaxial growth processes\, the material pr
 operties of complicated Si/SiGe multi-layer stacks used for complementary 
 field effect transistor (CFET) devices\, where gate-all-around nFETs and p
 FETs are stacked\, will be discussed. The given layer stack contains two d
 ifferent Ge concentrations and has been grown using conventional process g
 ases. A relatively high growth temperature is used to obtain acceptable Si
  and SiGe growth rates. 3D island growth has been suppressed for Ge concen
 trations up to 40%\, despite the rather high growth temperature. Excellent
  structural and optical material properties of the Si/SiGe multi-layer sta
 ck will be reported\, with up to 3 + 3 Si channels in the top and bottom p
 art of the stack\, respectively. The absence/presence of lattice defects h
 as also been verified by room-temperature photoluminescence measurements. 
 Photoluminescence measurements at low temperatures are used to study band-
 to-band luminescence from individual sub-layers and to illustrate the opti
 cal material quality of the CFET stack.\n\nVirtual: https://events.vtools.
 ieee.org/m/531995
LOCATION:Virtual: https://events.vtools.ieee.org/m/531995
ORGANIZER:richard.fung@ieee.org
SEQUENCE:45
SUMMARY:EDS Webinar: Evolution of metal-oxide-semiconductor device architec
 tures and the corresponding requirements on epitaxial growth processes
URL;VALUE=URI:https://events.vtools.ieee.org/m/531995
X-ALT-DESC:Description: &lt;br /&gt;&lt;h4 style=&quot;text-align: left\; line-height: 1\
 ;&quot;&gt;&lt;span style=&quot;font-family: arial\, helvetica\, sans-serif\;&quot;&gt;&lt;span style
 =&quot;font-size: 24px\;&quot;&gt;EDS Webinar:&lt;/span&gt;&lt;/span&gt;&lt;/h4&gt;\n&lt;h4 style=&quot;text-alig
 n: left\; line-height: 1\;&quot;&gt;&lt;span style=&quot;font-size: 18pt\;&quot;&gt;&lt;span style=&quot;f
 ont-family: &#39;Aptos Display&#39;\; color: black\;&quot;&gt;&lt;span style=&quot;font-size: 14pt
 \;&quot;&gt;&lt;em&gt;&lt;span style=&quot;font-family: &#39;Times New Roman&#39;\; color: black\;&quot;&gt;&lt;spa
 n style=&quot;font-family: arial\, helvetica\, sans-serif\;&quot;&gt;Evolution of metal
 -oxide-semiconductor device architectures and the corresponding requiremen
 ts on epitaxial growth processes&lt;/span&gt;&lt;/span&gt;&lt;/em&gt;&lt;/span&gt;&lt;/span&gt;&lt;/span&gt;&lt;/
 h4&gt;\n&lt;p style=&quot;text-align: justify\; line-height: 1.1\;&quot;&gt;&lt;span id=&quot;E240&quot; i
 s=&quot;&quot;&gt;After a short description of the evolution of metal-oxide-semiconduct
 or device architectures and the corresponding requirements on epitaxial gr
 owth processes\, the material properties of complicated Si/&lt;/span&gt;&lt;span id
 =&quot;E242&quot; is=&quot;&quot;&gt;SiGe&lt;/span&gt;&lt;span id=&quot;E244&quot; is=&quot;&quot;&gt; multi-layer stacks used fo
 r complementary field effect transistor (CFET) devices\, where gate-all-ar
 ound &lt;/span&gt;&lt;span id=&quot;E246&quot; is=&quot;&quot;&gt;nFETs&lt;/span&gt;&lt;span id=&quot;E248&quot; is=&quot;&quot;&gt; and &lt;
 /span&gt;&lt;span id=&quot;E250&quot; is=&quot;&quot;&gt;pFETs&lt;/span&gt;&lt;span id=&quot;E252&quot; is=&quot;&quot;&gt; are stacked
 \, will be discussed. The given layer stack contains two different Ge conc
 entrations and has been grown using conventional process gases. A relative
 ly high growth temperature is used to obtain acceptable Si and &lt;/span&gt;&lt;spa
 n id=&quot;E254&quot; is=&quot;&quot;&gt;SiGe&lt;/span&gt;&lt;span id=&quot;E256&quot; is=&quot;&quot;&gt; growth rates. 3D islan
 d growth has been suppressed for Ge concentrations up to 40%\, despite the
  rather high growth temperature. Excellent structural and optical material
  properties of the Si/&lt;/span&gt;&lt;span id=&quot;E258&quot; is=&quot;&quot;&gt;SiGe&lt;/span&gt;&lt;span id=&quot;E2
 60&quot; is=&quot;&quot;&gt; multi-layer stack will be reported\, with up to 3 + 3 Si channe
 ls in the top and bottom part of the stack\, respectively. The absence/pre
 sence of lattice defects has also been verified by room-temperature photol
 uminescence measurements. Photoluminescence measurements at low temperatur
 es are used to study band-to-band luminescence from individual sub-layers 
 and to illustrate the optical material quality of the CFET stack.&lt;/span&gt;&lt;/
 p&gt;&lt;br /&gt;&lt;br /&gt;Agenda: &lt;br /&gt;&lt;h4 style=&quot;text-align: left\; line-height: 1\;
 &quot;&gt;&lt;span style=&quot;font-family: arial\, helvetica\, sans-serif\;&quot;&gt;&lt;span style=
 &quot;font-size: 24px\;&quot;&gt;EDS Webinar:&lt;/span&gt;&lt;/span&gt;&lt;/h4&gt;\n&lt;h4 style=&quot;text-align
 : left\; line-height: 1\;&quot;&gt;&lt;span style=&quot;font-size: 18pt\;&quot;&gt;&lt;span style=&quot;fo
 nt-family: &#39;Aptos Display&#39;\; color: black\;&quot;&gt;&lt;span style=&quot;font-size: 14pt\
 ;&quot;&gt;&lt;em&gt;&lt;span style=&quot;font-family: &#39;Times New Roman&#39;\; color: black\;&quot;&gt;&lt;span
  style=&quot;font-family: arial\, helvetica\, sans-serif\;&quot;&gt;Evolution of metal-
 oxide-semiconductor device architectures and the corresponding requirement
 s on epitaxial growth processes&lt;/span&gt;&lt;/span&gt;&lt;/em&gt;&lt;/span&gt;&lt;/span&gt;&lt;/span&gt;&lt;/h
 4&gt;\n&lt;p id=&quot;E237&quot; class=&quot;x-scope qowt-word-para-0&quot; is=&quot;&quot;&gt;&lt;span id=&quot;E238&quot; is
 =&quot;&quot;&gt;Abstract:&lt;/span&gt;&lt;/p&gt;\n&lt;p id=&quot;E239&quot; class=&quot;x-scope qowt-word-para-0&quot; is
 =&quot;&quot;&gt;&lt;span id=&quot;E240&quot; is=&quot;&quot;&gt;After a short description of the evolution of me
 tal-oxide-semiconductor device architectures and the corresponding require
 ments on epitaxial growth processes\, the material properties of complicat
 ed Si/&lt;/span&gt;&lt;span id=&quot;E242&quot; is=&quot;&quot;&gt;SiGe&lt;/span&gt;&lt;span id=&quot;E244&quot; is=&quot;&quot;&gt; multi
 -layer stacks used for complementary field effect transistor (CFET) device
 s\, where gate-all-around &lt;/span&gt;&lt;span id=&quot;E246&quot; is=&quot;&quot;&gt;nFETs&lt;/span&gt;&lt;span i
 d=&quot;E248&quot; is=&quot;&quot;&gt; and &lt;/span&gt;&lt;span id=&quot;E250&quot; is=&quot;&quot;&gt;pFETs&lt;/span&gt;&lt;span id=&quot;E25
 2&quot; is=&quot;&quot;&gt; are stacked\, will be discussed. The given layer stack contains 
 two different Ge concentrations and has been grown using conventional proc
 ess gases. A relatively high growth temperature is used to obtain acceptab
 le Si and &lt;/span&gt;&lt;span id=&quot;E254&quot; is=&quot;&quot;&gt;SiGe&lt;/span&gt;&lt;span id=&quot;E256&quot; is=&quot;&quot;&gt; g
 rowth rates. 3D island growth has been suppressed for Ge concentrations up
  to 40%\, despite the rather high growth temperature. Excellent structural
  and optical material properties of the Si/&lt;/span&gt;&lt;span id=&quot;E258&quot; is=&quot;&quot;&gt;Si
 Ge&lt;/span&gt;&lt;span id=&quot;E260&quot; is=&quot;&quot;&gt; multi-layer stack will be reported\, with 
 up to 3 + 3 Si channels in the top and bottom part of the stack\, respecti
 vely. The absence/presence of lattice defects has also been verified by ro
 om-temperature photoluminescence measurements. Photoluminescence measureme
 nts at low temperatures are used to study band-to-band luminescence from i
 ndividual sub-layers and to illustrate the optical material quality of the
  CFET stack.&lt;/span&gt;&lt;/p&gt;
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