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DTSTART:20260308T030000
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DTSTAMP:20260307T171939Z
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DTSTART;TZID=America/Los_Angeles:20260303T180000
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DESCRIPTION:The Making of a Chip is an introductory technical and career-fo
 cused session designed to provide participants with a comprehensive overvi
 ew of the complete ASIC development lifecycle. The event will guide attend
 ees through each critical phase of chip creation\, starting from system an
 d ASIC/VLSI specifications\, progressing through design and verification\,
  and concluding with post-silicon validation.\n\nParticipants will gain in
 sights into how real-world requirements are translated into silicon-ready 
 designs\, the role of RTL design and functional verification\, and the imp
 ortance of validation after fabrication to ensure performance\, reliabilit
 y\, and compliance. In addition to the technical flow\, the session will h
 ighlight current industry practices\, tools\, and skills required at each 
 stage of the semiconductor lifecycle.\n\nThe event will also focus on care
 er opportunities for graduates in the semiconductor industry\, outlining v
 arious job roles such as ASIC/VLSI design engineer\, verification engineer
 \, validation engineer\, and related entry-level positions. Industry expec
 tations\, essential skill sets\, and career pathways will be discussed to 
 help students and early-career professionals prepare for roles in chip des
 ign and development.\n\nThis session is ideal for engineering students and
  graduates who are interested in understanding ASIC/VLSI design workflows 
 and exploring career opportunities in the semiconductor domain.\n\nAgenda:
  \nAgenda\n\n6:00 PM – 6:15 PM\nWelcome Note &amp; Event Overview\n\n6:15 PM
  – 7:15 PM\nThe Making of a Chip: Technology\, Tools\, and Careers - Big
  picture\n\nSpeakers - Jigneshkumar Patel (AMD)\, Venupradeepa Kolari (Int
 el) and Amiraj Nigam (Intel)\, Lalatendu Satpathy (Intel)\n\n7:15 PM – 8
 :00 PM\nResume Review &amp; 1-to-1 Mentoring with Graduates\n\nJigneshkumar Pa
 tel (AMD)\, Venupradeepa Kolari (Intel)\, Amiraj Nigam (Intel)\, Lalatendu
  Satpathy (Intel)\, Arvind Akula (Rate Inc)\, Anurag (Intel)\n\n🍕 Pizza
  will be served.\n\nIf you’re looking for a mentor or hoping to expand y
 our professional network\, this is the perfect chance to connect and learn
  from experts and peers.\n\nRoom: 1015\, Bldg: Riverside Hall\, 6000 J Str
 eet\, Sacramento\, California\, United States\, 95819
LOCATION:Room: 1015\, Bldg: Riverside Hall\, 6000 J Street\, Sacramento\, C
 alifornia\, United States\, 95819
ORGANIZER:venuskolari@gmail.com, jigarmicro@gmail.com
SEQUENCE:44
SUMMARY:The Making of a Chip: Technology\, Tools\, and Careers
URL;VALUE=URI:https://events.vtools.ieee.org/m/532357
X-ALT-DESC:Description: &lt;br /&gt;&lt;p data-start=&quot;136&quot; data-end=&quot;538&quot;&gt;&lt;strong&gt;Th
 e Making of a Chip is an introductory technical and career-focused session
 &lt;/strong&gt; designed to provide participants with a comprehensive overview o
 f the complete ASIC development lifecycle. The event will guide attendees 
 through each critical phase of chip creation\, starting from system and AS
 IC/VLSI specifications\, progressing through design and verification\, and
  concluding with post-silicon validation.&lt;/p&gt;\n&lt;p data-start=&quot;540&quot; data-en
 d=&quot;965&quot;&gt;Participants will gain insights into how real-world requirements a
 re translated into silicon-ready designs\, the role of RTL design and func
 tional verification\, and the importance of validation after fabrication t
 o ensure performance\, reliability\, and compliance. In addition to the te
 chnical flow\, the session will highlight current industry practices\, too
 ls\, and skills required at each stage of the semiconductor lifecycle.&lt;/p&gt;
 \n&lt;p data-start=&quot;967&quot; data-end=&quot;1383&quot;&gt;The event will also focus on &lt;strong
  data-start=&quot;996&quot; data-end=&quot;1034&quot;&gt;career opportunities for graduates&lt;/stro
 ng&gt; in the semiconductor industry\, outlining various job roles such as AS
 IC/VLSI design engineer\, verification engineer\, validation engineer\, an
 d related entry-level positions. Industry expectations\, essential skill s
 ets\, and career pathways will be discussed to help students and early-car
 eer professionals prepare for roles in chip design and development.&lt;/p&gt;\n&lt;
 p data-start=&quot;1385&quot; data-end=&quot;1567&quot;&gt;This session is ideal for engineering 
 students and graduates who are interested in understanding &lt;strong&gt;ASIC/VL
 SI design workflows&lt;/strong&gt; and exploring &lt;strong&gt;career opportunities&lt;/s
 trong&gt; in the semiconductor domain.&lt;/p&gt;&lt;br /&gt;&lt;br /&gt;Agenda: &lt;br /&gt;&lt;h3 data-
 start=&quot;140&quot; data-end=&quot;164&quot;&gt;&lt;strong data-start=&quot;144&quot; data-end=&quot;164&quot;&gt;Agenda&lt;
 /strong&gt;&lt;/h3&gt;\n&lt;p data-start=&quot;166&quot; data-end=&quot;219&quot;&gt;&lt;strong data-start=&quot;166&quot;
  data-end=&quot;187&quot;&gt;6:00 PM &amp;ndash\; 6:15 PM&lt;/strong&gt;&lt;br data-start=&quot;187&quot; data
 -end=&quot;190&quot;&gt;Welcome Note &amp;amp\; Event Overview&lt;/p&gt;\n&lt;p data-start=&quot;336&quot; dat
 a-end=&quot;450&quot;&gt;&lt;strong data-start=&quot;336&quot; data-end=&quot;357&quot;&gt;6:15 PM &amp;ndash\; 7:15 
 PM&lt;/strong&gt;&lt;br data-start=&quot;357&quot; data-end=&quot;360&quot;&gt;The Making of a Chip: Techn
 ology\, Tools\, and Careers - Big picture&amp;nbsp\;&lt;/p&gt;\n&lt;p data-start=&quot;336&quot; 
 data-end=&quot;450&quot;&gt;Speakers - Jigneshkumar Patel (AMD)\, Venupradeepa Kolari (
 Intel) and Amiraj Nigam (Intel)\, Lalatendu Satpathy (Intel)&lt;/p&gt;\n&lt;p data-
 start=&quot;561&quot; data-end=&quot;683&quot;&gt;&lt;strong data-start=&quot;561&quot; data-end=&quot;582&quot;&gt;7:15 PM
  &amp;ndash\; 8:00 PM&lt;/strong&gt;&lt;br data-start=&quot;582&quot; data-end=&quot;585&quot;&gt;Resume Revie
 w &amp;amp\; 1-to-1 Mentoring with Graduates&lt;/p&gt;\n&lt;p data-start=&quot;623&quot; data-end
 =&quot;651&quot;&gt;Jigneshkumar Patel (AMD)\, Venupradeepa Kolari (Intel)\, Amiraj Nig
 am (Intel)\, Lalatendu Satpathy (Intel)\, Arvind Akula (Rate Inc)\, Anurag
  (Intel)&lt;/p&gt;\n&lt;p data-start=&quot;623&quot; data-end=&quot;651&quot;&gt;🍕&amp;nbsp\;&lt;strong data-s
 tart=&quot;626&quot; data-end=&quot;651&quot;&gt;Pizza will be served.&lt;/strong&gt;&lt;/p&gt;\n&lt;p data-star
 t=&quot;653&quot; data-end=&quot;812&quot;&gt;If you&amp;rsquo\;re looking for a &lt;strong data-start=&quot;
 677&quot; data-end=&quot;687&quot;&gt;mentor&lt;/strong&gt; or hoping to &lt;strong data-start=&quot;701&quot; 
 data-end=&quot;737&quot;&gt;expand your professional network&lt;/strong&gt;\, this is the per
 fect chance to connect and learn from experts and peers.&lt;/p&gt;
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