BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:America/Los_Angeles BEGIN:DAYLIGHT DTSTART:20260308T030000 TZOFFSETFROM:-0800 TZOFFSETTO:-0700 RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3 TZNAME:PDT END:DAYLIGHT BEGIN:STANDARD DTSTART:20251102T010000 TZOFFSETFROM:-0700 TZOFFSETTO:-0800 RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11 TZNAME:PST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20260128T002500Z UID:49958E8D-DB42-445E-A225-A05396864E74 DTSTART;TZID=America/Los_Angeles:20260120T173000 DTEND;TZID=America/Los_Angeles:20260120T193000 DESCRIPTION:This talk will provide an overview of radiation effects in inte grated circuits and discuss radiation\nhardening techniques. The talk will focus on single-event effects (SEE) and will review the impact of\nSEE in storage and combinational logic circuits. The semiconductor industry has been striving to keep up\nwith Moore’s law scaling predictions through i nnovative process solutions from planar to FinFET and to\ncurrent nanoshee t processes. This has helped develop high-performance application specific integrated\ncircuits (ASIC) to suit a variety of space and terrestrial ap plications. On the other hand\, with technology\nscaling and the associate d increase in packing densities and reduction in operating voltages\, the critical\ncharge needed to cause single-event effects in digital circuits has decreased significantly resulting in\nincreased vulnerability to radia tion. This talk will review hardening-by-design approaches used for\noverc oming single-events in memories\, latches and logic circuits. Error correc tion techniques for\nmemories along with spacial- and time- redundancy bas ed approaches for latches and logic circuits will\nbe presented. Recent ad vancement in the radiation-tolerant design approaches that tradeoff perfor mance\npenalty with the extent of radiation tolerance to suit different ap plications will be discussed along with the\nperformance overhead vs. radi ation tolerance comparisons. Finally\, the talk will review scaling trends and\nbias dependence of single-event upset rates from planar to FinFET pr ocesses with an emphasis on the\nopportunities and challenges for radiatio n hardening in highly scaled technologies.\n\nSpeaker(s): Balaji\n\nAgenda : \nPresenter: Dr Balaji Narasimhan\, Reliability Team Lead\, Broadcom.\nT itle: Designing ICs for Rad Hard applications.\nDate: 5:30pm\, January 20t h\n\n15101 Alton Parkway\, Irvine\, California\, United States\, 92618 LOCATION:15101 Alton Parkway\, Irvine\, California\, United States\, 92618 ORGANIZER:rohit.pal@gmail.com SEQUENCE:17 SUMMARY:Designing ICs for Rad Hard applications URL;VALUE=URI:https://events.vtools.ieee.org/m/532588 X-ALT-DESC:Description: <br /><p>This talk will provide an overview of radi ation effects in integrated circuits and discuss radiation<br>hardening te chniques. The talk will focus on single-event effects (SEE) and will revie w the impact of<br>SEE in storage and combinational logic circuits. The se miconductor industry has been striving to keep up<br>with Moore&rsquo\;s l aw scaling predictions through innovative process solutions from planar to FinFET and to<br>current nanosheet processes. This has helped develop hig h-performance application specific integrated<br>circuits (ASIC) to suit a variety of space and terrestrial applications. On the other hand\, with t echnology<br>scaling and the associated increase in packing densities and reduction in operating voltages\, the critical<br>charge needed to cause s ingle-event effects in digital circuits has decreased significantly result ing in<br>increased vulnerability to radiation. This talk will review hard ening-by-design approaches used for<br>overcoming single-events in memorie s\, latches and logic circuits. Error correction techniques for<br>memorie s along with spacial- and time- redundancy based approaches for latches an d logic circuits will<br>be presented. Recent advancement in the radiation -tolerant design approaches that tradeoff performance<br>penalty with the extent of radiation tolerance to suit different applications will be discu ssed along with the<br>performance overhead vs. radiation tolerance compar isons. Finally\, the talk will review scaling trends and<br>bias dependenc e of single-event upset rates from planar to FinFET processes with an emph asis on the<br>opportunities and challenges for radiation hardening in hig hly scaled technologies.</p><br /><br />Agenda: <br /><div>Presenter: Dr B alaji Narasimhan\, Reliability&nbsp\;Team Lead\, Broadcom.</div>\n<div>Tit le: Designing ICs for Rad Hard applications.</div>\n<div>Date: 5:30pm\, Ja nuary 20th</div> END:VEVENT END:VCALENDAR