BEGIN:VCALENDAR
VERSION:2.0
PRODID:IEEE vTools.Events//EN
CALSCALE:GREGORIAN
BEGIN:VTIMEZONE
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TZOFFSETFROM:-0500
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RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3
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BEGIN:STANDARD
DTSTART:20251102T010000
TZOFFSETFROM:-0400
TZOFFSETTO:-0500
RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11
TZNAME:EST
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20260212T182044Z
UID:E0063F96-2E2E-47D0-9F98-51776B73EC0A
DTSTART;TZID=America/New_York:20260211T100000
DTEND;TZID=America/New_York:20260211T113000
DESCRIPTION:The aim of this presentation is to introduce the basics and var
 ious practical illustrations of advanced ADC enhancement techniques in a n
 utshell. With applications pushing for higher resolutions & data-rates\, a
 nd technology-scaling favoring digital design\, the use of digital techniq
 ues to enhance ADC performance is inevitable. This talk will first summari
 ze trends and trade-offs regarding the use of these digital-intensive tech
 niques before illustrating some popular and recent examples from literatur
 e\, including calibration and enhancement techniques as well as digitally-
 inspired analog circuit design. Besides that\, an outlook is given regardi
 ng future challenges and opportunities in advanced CMOS technologies.\n\nS
 peaker(s): Pieter\, \n\nAgenda: \n10.00-11.30 Presentation by Pieter Harpe
  plus Q&A with the attendees\n\nRoom: 3142\, Bldg: EIT\, University of Wat
 erloo\, 200 University Avenue West\, Waterloo\, Ontario\, Canada\, N2L 3G4
LOCATION:Room: 3142\, Bldg: EIT\, University of Waterloo\, 200 University A
 venue West\, Waterloo\, Ontario\, Canada\, N2L 3G4
ORGANIZER:jrlong@uwaterloo.ca
SEQUENCE:52
SUMMARY:Analog-to-Digital Converter Enhancement Techniques in Advanced CMOS
  Technologies
URL;VALUE=URI:https://events.vtools.ieee.org/m/533701
X-ALT-DESC:Description: <br /><p>The aim of this presentation is to introdu
 ce the basics and various practical illustrations of advanced ADC enhancem
 ent techniques in a nutshell. With applications pushing for higher resolut
 ions &amp\; data-rates\, and technology-scaling favoring digital design\, 
 the use of digital techniques to enhance ADC performance is inevitable. Th
 is talk will first summarize trends and trade-offs regarding the use of th
 ese digital-intensive techniques before illustrating some popular and rece
 nt examples from literature\, including calibration and enhancement techni
 ques as well as digitally-inspired analog circuit design. Besides that\, a
 n outlook is given regarding future challenges and opportunities in advanc
 ed CMOS technologies.</p><br /><br />Agenda: <br /><p>10.00-11.30 Presenta
 tion by Pieter Harpe plus Q&amp\;A with the attendees</p>
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