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PRODID:IEEE vTools.Events//EN
CALSCALE:GREGORIAN
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TZID:America/Chicago
BEGIN:DAYLIGHT
DTSTART:20260308T030000
TZOFFSETFROM:-0600
TZOFFSETTO:-0500
RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3
TZNAME:CDT
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BEGIN:STANDARD
DTSTART:20251102T010000
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TZOFFSETTO:-0600
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BEGIN:VEVENT
DTSTAMP:20260201T161938Z
UID:8F4C96AA-8F68-4CDE-8C2C-EE7658A7FBFA
DTSTART;TZID=America/Chicago:20260129T120000
DTEND;TZID=America/Chicago:20260129T130000
DESCRIPTION:Data Center CPU\, GPU and AI accelerators have evolved from mon
 olithic System-on-Chip designs to heterogenous System-of-Chiplets to enabl
 e “More-than-Moore” scaling of system-level performance and energy eff
 iciency at lower costs. This presentation highlights importance of interdi
 sciplinary System-Technology Co-Optimizations (STCO) for architecting such
  heterogenous System-of-Chiplets. We will discuss architecture and design 
 considerations for optimizing compute\, memory and interconnect components
 \, as well as trade-offs and co-optimization opportunities with process/pa
 ckaging technologies\, power delivery\, thermals and system architectures.
  We will also highlight future trends and innovations required to drive co
 ntinued performance and efficiency improvements for the AI era.\n\nVirtual
 : https://events.vtools.ieee.org/m/534322
LOCATION:Virtual: https://events.vtools.ieee.org/m/534322
ORGANIZER:ravi_kishorek@yahoo.com
SEQUENCE:23
SUMMARY:IEEE SSCS/CAS CTX Feed Your Mind Webinar: Architecting Heterogenous
  System-of-Chiplets for Data Center and AI Era
URL;VALUE=URI:https://events.vtools.ieee.org/m/534322
X-ALT-DESC:Description: &lt;br /&gt;&lt;p class=&quot;MsoNormal&quot;&gt;Data Center CPU\, GPU an
 d AI accelerators have evolved from monolithic System-on-Chip designs to h
 eterogenous System-of-Chiplets to enable &amp;ldquo\;More-than-Moore&amp;rdquo\; s
 caling of system-level performance and energy efficiency at lower costs. T
 his presentation highlights importance of interdisciplinary System-Technol
 ogy Co-Optimizations (STCO) for architecting such heterogenous System-of-C
 hiplets. We will discuss architecture and design considerations for optimi
 zing compute\, memory and interconnect components\, as well as trade-offs 
 and co-optimization opportunities with process/packaging technologies\, po
 wer delivery\, thermals and system architectures. We will also highlight f
 uture trends and innovations required to drive continued performance and e
 fficiency improvements for the AI era.&lt;/p&gt;
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