BEGIN:VCALENDAR
VERSION:2.0
PRODID:IEEE vTools.Events//EN
CALSCALE:GREGORIAN
BEGIN:VTIMEZONE
TZID:Asia/Kolkata
BEGIN:STANDARD
DTSTART:19451014T230000
TZOFFSETFROM:+0630
TZOFFSETTO:+0530
TZNAME:IST
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BEGIN:VEVENT
DTSTAMP:20260712T094211Z
UID:FED95DCD-7078-4C0B-9639-7347083DFC42
DTSTART;TZID=Asia/Kolkata:20260221T183000
DTEND;TZID=Asia/Kolkata:20260620T170000
DESCRIPTION:The “EDA Toolsmith” program was organized to create awarene
 ss and generate interest in the development and use of open-source Electro
 nic Design Automation (EDA) tools for integrated circuit (IC) design. The 
 program aimed to encourage prospective engineers to move beyond being “t
 ool users” and become “tool developers”.\n\nAs part of the program\,
  participants learned to develop a simple Verilog compiler using the open-
 source tools Flex and Bison. The participants included mainly engineering 
 students\, along with a couple of faculty members\, from various engineeri
 ng colleges.\n\nThe program was conducted through a series of online lectu
 res held on Saturdays\, followed by a project phase in which the participa
 nts applied the concepts they had learned. The completed projects were eva
 luated by a panel of judges\, and the best projects were recognized with p
 rizes.\n\n[]\n\nSpeaker(s): Aloke Das\n\nBangalore Institute of Technology
 \, Bangalore\, Karnataka\, India\, 560004
LOCATION:Bangalore Institute of Technology\, Bangalore\, Karnataka\, India\
 , 560004
ORGANIZER:asgirish13@gmail.com
SEQUENCE:16
SUMMARY:IEEE CEDA EDA Toolsmith – From Algorithms to Implementation
URL;VALUE=URI:https://events.vtools.ieee.org/m/538161
X-ALT-DESC:Description: &lt;br /&gt;&lt;p class=&quot;MsoNormal&quot; style=&quot;text-align: justi
 fy\; margin: 12.0pt 0cm 12.0pt 0cm\;&quot;&gt;&lt;span style=&quot;font-size: 13.0pt\; lin
 e-height: 107%\; mso-ansi-language: EN-IN\;&quot;&gt;The &amp;ldquo\;EDA Toolsmith&amp;rdq
 uo\; program was organized to create awareness and generate interest in th
 e development and use of open-source Electronic Design Automation (EDA) to
 ols for integrated circuit (IC) design. The program aimed to encourage pro
 spective engineers to move beyond being &amp;ldquo\;&lt;em&gt;tool users&amp;rdquo\;&lt;/em
 &gt; and become &amp;ldquo\;&lt;em&gt;tool developers&amp;rdquo\;&lt;/em&gt;.&lt;/span&gt;&lt;/p&gt;\n&lt;p clas
 s=&quot;MsoNormal&quot; style=&quot;text-align: justify\; margin: 12.0pt 0cm 12.0pt 0cm\;
 &quot;&gt;&lt;span style=&quot;font-size: 13.0pt\; line-height: 107%\; mso-ansi-language: 
 EN-IN\;&quot;&gt;As part of the program\, participants learned to develop a simple
  Verilog compiler using the open-source tools Flex and Bison. The particip
 ants included mainly engineering students\, along with a couple of faculty
  members\, from various engineering colleges.&lt;/span&gt;&lt;/p&gt;\n&lt;p&gt;&lt;span style=&quot;
 font-size: 13.0pt\; line-height: 107%\; font-family: &#39;Calibri&#39;\,sans-serif
 \; mso-fareast-font-family: Calibri\; mso-ansi-language: EN-IN\; mso-farea
 st-language: EN-IN\; mso-bidi-language: AR-SA\;&quot;&gt;The program was conducted
  through a series of online lectures held on Saturdays\, followed by a pro
 ject phase in which the participants applied the concepts they had learned
 . The completed projects were evaluated by a panel of judges\, and the bes
 t projects were recognized with prizes.&lt;/span&gt;&lt;/p&gt;\n&lt;table style=&quot;border-c
 ollapse: collapse\; width: 100%\;&quot; border=&quot;1&quot;&gt;&lt;colgroup&gt;&lt;col style=&quot;width:
  33.3013%\;&quot;&gt;&lt;col style=&quot;width: 33.3013%\;&quot;&gt;&lt;col style=&quot;width: 33.3013%\;&quot;
 &gt;&lt;/colgroup&gt;\n&lt;tbody&gt;\n&lt;tr&gt;\n&lt;td&gt;&lt;img src=&quot;https://events.vtools.ieee.org/
 vtools_ui/media/display/cd0e2d22-1c29-4558-899f-e91f78a7c2d6&quot; width=&quot;330&quot; 
 height=&quot;186&quot;&gt;&lt;/td&gt;\n&lt;td&gt;&lt;img src=&quot;https://events.vtools.ieee.org/vtools_ui
 /media/display/d80fa9cd-0c75-477e-9a1a-0461307b3f3d&quot; width=&quot;330&quot; height=&quot;2
 49&quot;&gt;&lt;/td&gt;\n&lt;td&gt;&lt;img src=&quot;https://events.vtools.ieee.org/vtools_ui/media/di
 splay/5d0f014b-9a48-4934-8ab2-65e948a22ef4&quot; width=&quot;330&quot; height=&quot;248&quot;&gt;&lt;/td&gt;
 \n&lt;/tr&gt;\n&lt;tr&gt;\n&lt;td&gt;&lt;img src=&quot;https://events.vtools.ieee.org/vtools_ui/medi
 a/display/48f8a963-8637-4a6b-b72f-790db29087af&quot; width=&quot;330&quot; height=&quot;248&quot;&gt;&lt;
 /td&gt;\n&lt;td&gt;&lt;img src=&quot;https://events.vtools.ieee.org/vtools_ui/media/display
 /bca7ced7-548e-4664-bd04-cb9e0725e7a6&quot; width=&quot;330&quot; height=&quot;248&quot;&gt;&lt;/td&gt;\n&lt;td
 &gt;\n&lt;p&gt;&amp;nbsp\;&lt;/p&gt;\n&lt;p&gt;&lt;img src=&quot;https://events.vtools.ieee.org/vtools_ui/m
 edia/display/daa2cc63-9cb4-4236-84fe-6c59e47489a4&quot; alt=&quot;&quot; width=&quot;330&quot; heig
 ht=&quot;249&quot;&gt;&lt;/p&gt;\n&lt;/td&gt;\n&lt;/tr&gt;\n&lt;/tbody&gt;\n&lt;/table&gt;
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