BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:America/Los_Angeles BEGIN:DAYLIGHT DTSTART:20260308T030000 TZOFFSETFROM:-0800 TZOFFSETTO:-0700 RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3 TZNAME:PDT END:DAYLIGHT BEGIN:STANDARD DTSTART:20261101T010000 TZOFFSETFROM:-0700 TZOFFSETTO:-0800 RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11 TZNAME:PST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20260410T201603Z UID:F1F4C8EB-22F4-4CFD-A46B-82DC9E4E0E9A DTSTART;TZID=America/Los_Angeles:20260410T120000 DTEND;TZID=America/Los_Angeles:20260410T130000 DESCRIPTION:[]Chiplets have become a compelling approach to scaling and het erogeneous integration e.g. integrating workload-specific processors and m assive bandwidth memory systems into computing systems\; integrating die f rom multiple function-optimized process nodes into one product\; integrati ng silicon from multiple businesses into one product. Chiplet-based produc ts have been produced in high volume by multiple companies using proprieta ry chiplet ecosystems. Recently\, the community has proposed several new s tandards (e.g.\, UCIe) to facilitate integration and interoperability of a ny compliant chiplet. Hyperscalers (e.g.\, Google\, Amazon) are actively d esigning high volume products with chiplets through these open interfaces. Other communities are exploring the end-to-end workflow and tooling to as semble chiplet-based products. High performance computing can benefit from this trend. However\, the performance\, power\, and thermal requirements unique to HPC\, present many challenges to realizing a vision for affordab le\, modular HPC using this new approach. Architectural modeling and simul ation will play a critical role in pathfinding for this new potential dire ction for HPC beyond Exascale.\n\nSpeaker(s): John Shalf\, \n\nAgenda: \ns ee ‘location’ for WebEx details\n\nVirtual: https://events.vtools.ieee .org/m/539463 LOCATION:Virtual: https://events.vtools.ieee.org/m/539463 ORGANIZER:p.wesling@ieee.org SEQUENCE:20 SUMMARY:Using Architectural Simulation to Investigate Chiplets for Scalable and Cost Effective HPC Beyond Exascale URL;VALUE=URI:https://events.vtools.ieee.org/m/539463 X-ALT-DESC:Description: <br /><p><img style="float: right\;" src="https://e vents.vtools.ieee.org/vtools_ui/media/display/fb6e6e71-fb09-46a4-8fe9-864d 3f45e019" alt="" width="500" height="250">Chiplets have become a compellin g approach to scaling and heterogeneous integration e.g. integrating workl oad-specific processors and massive bandwidth memory systems into computin g systems\; integrating die from multiple function-optimized process nodes into one product\; integrating silicon from multiple businesses into one product. Chiplet-based products have been produced in high volume by multi ple companies using proprietary chiplet ecosystems. Recently\, the communi ty has proposed several new standards (e.g.\, UCIe) to facilitate integrat ion and interoperability of any compliant chiplet. Hyperscalers (e.g.\, Go ogle\, Amazon) are actively designing high volume products with chiplets t hrough these open interfaces. Other communities are exploring the end-to-e nd workflow and tooling to assemble chiplet-based products. High performan ce computing can benefit from this trend. However\, the performance\, powe r\, and thermal requirements unique to HPC\, present many challenges to re alizing a vision for affordable\, modular HPC using this new approach. Arc hitectural modeling and simulation will play a critical role in pathfindin g for this new potential direction for HPC beyond Exascale.</p><br /><br / >Agenda: <br /><p>see &lsquo\;location&rsquo\; for WebEx details</p> END:VEVENT END:VCALENDAR