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PRODID:IEEE vTools.Events//EN
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TZID:Asia/Kolkata
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DTSTART:19451014T230000
TZOFFSETFROM:+0630
TZOFFSETTO:+0530
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BEGIN:VEVENT
DTSTAMP:20260317T090356Z
UID:DC8D0672-1A0B-4D91-B56C-86489886CADF
DTSTART;TZID=Asia/Kolkata:20260306T150000
DTEND;TZID=Asia/Kolkata:20260306T160000
DESCRIPTION:The IEEE CEDA DSCE Student Chapter organized a technical talk t
 itled “ASIC Design Beyond Theory: Industry Experience and Practice” on
  6th March 2026 at the Department of Electronics and Communication Enginee
 ring\, Dayananda Sagar College of Engineering. The objective of the event 
 was to provide students with practical insights into Application-Specific 
 Integrated Circuit (ASIC) design and to bridge the gap between academic le
 arning and real-world semiconductor industry practices.\n\nThe session was
  delivered by Mr. Palash Khandale\, an industry professional with extensiv
 e experience in semiconductor design and ASIC development. The event began
  with a warm welcome extended to the resource person\, faculty members\, a
 nd participating students. The speaker was formally introduced\, highlight
 ing his expertise in ASIC design flow and his contributions to the semicon
 ductor industry.\n\nAs a gesture of appreciation\, the organizing team pre
 sented a sapling to the resource person\, symbolizing respect and gratitud
 e. During the session\, the resource person\, symbolizing respect and grat
 itude. During the session\, the speaker discussed various aspects of ASIC 
 design including the industry workflow\, practical design challenges\, ver
 ification processes\, and emerging opportunities in the semiconductor fiel
 d. He also emphasized the importance of strong fundamentals in digital des
 ign and verification for students aspiring to build careers in VLSI and se
 miconductor industries.\n\nThe talk was highly interactive\, with students
  actively engaging in discussions and asking questions related to ASIC des
 ign tools\, industry expectations\, and career opportunities. The session 
 provided valuable exposure to real-world engineering practices and motivat
 ed students to explore deeper knowledge in VLSI and semiconductor technolo
 gies.\n\nOverall\, the event was informative and successful\, benefiting s
 tudents by providing practical insights and guidance from an experienced i
 ndustry professional.\n\n[]\n\n[]	[]	[]\n\nSpeaker(s): Palash Khandale\n\n
 Agenda: \n3:30 PM – 3:40 PM\nWelcome Address and Introduction of the Spe
 aker\n\n3:40 PM – 4:50 PM\nTechnical Talk by Mr. Palash Khandale\nTopic:
  ASIC Design Beyond Theory: Industry Experience and Practice\n\n4:50 PM 
 – 5:00 PM\nInteractive Q&amp;A Session\n\n5:00 PM\nVote of Thanks and Felici
 tation\n\nBuilding no 17\, Electronics Block\, DSCE campus\, Kumaraswamy l
 ayout\, Bangalore\, Karnataka\, India
LOCATION:Building no 17\, Electronics Block\, DSCE campus\, Kumaraswamy lay
 out\, Bangalore\, Karnataka\, India
ORGANIZER:avamsikrishna@ieee.org
SEQUENCE:7
SUMMARY:A Technical Talk on “ASIC Design Beyond Theory: Industry Experien
 ce and Practice”
URL;VALUE=URI:https://events.vtools.ieee.org/m/543833
X-ALT-DESC:Description: &lt;br /&gt;&lt;p dir=&quot;ltr&quot;&gt;The IEEE CEDA DSCE Student Chapt
 er organized a technical talk titled &amp;ldquo\;ASIC Design Beyond Theory: In
 dustry Experience and Practice&amp;rdquo\; on 6th March 2026 at the Department
  of Electronics and Communication Engineering\, Dayananda Sagar College of
  Engineering. The objective of the event was to provide students with prac
 tical insights into Application-Specific Integrated Circuit (ASIC) design 
 and to bridge the gap between academic learning and real-world semiconduct
 or industry practices.&lt;/p&gt;\n&lt;p dir=&quot;ltr&quot;&gt;The session was delivered by Mr. 
 Palash Khandale\, an industry professional with extensive experience in se
 miconductor design and ASIC development. The event began with a warm welco
 me extended to the resource person\, faculty members\, and participating s
 tudents. The speaker was formally introduced\, highlighting his expertise 
 in ASIC design flow and his contributions to the semiconductor industry.&lt;/
 p&gt;\n&lt;p dir=&quot;ltr&quot;&gt;As a gesture of appreciation\, the organizing team presen
 ted a sapling to the resource person\, symbolizing respect and gratitude. 
 During the session\, the resource person\, symbolizing respect and gratitu
 de. During the session\, the speaker discussed various aspects of ASIC des
 ign including the industry workflow\, practical design challenges\, verifi
 cation processes\, and emerging opportunities in the semiconductor field. 
 He also emphasized the importance of strong fundamentals in digital design
  and verification for students aspiring to build careers in VLSI and semic
 onductor industries.&lt;/p&gt;\n&lt;p dir=&quot;ltr&quot;&gt;The talk was highly interactive\, w
 ith students actively engaging in discussions and asking questions related
  to ASIC design tools\, industry expectations\, and career opportunities. 
 The session provided valuable exposure to real-world engineering practices
  and motivated students to explore deeper knowledge in VLSI and semiconduc
 tor technologies.&lt;/p&gt;\n&lt;p dir=&quot;ltr&quot;&gt;Overall\, the event was informative an
 d successful\, benefiting students by providing practical insights and gui
 dance from an experienced industry professional.&lt;/p&gt;\n&lt;p style=&quot;text-align
 : center\;&quot; data-start=&quot;1291&quot; data-end=&quot;1418&quot;&gt;&lt;img src=&quot;https://events.vto
 ols.ieee.org/vtools_ui/media/display/944f0a8b-0b00-460f-aaa0-ca2395eea8d5&quot;
  alt=&quot;&quot; width=&quot;574&quot; height=&quot;812&quot;&gt;&lt;/p&gt;\n&lt;table style=&quot;border-collapse: coll
 apse\; width: 100%\;&quot; border=&quot;1&quot;&gt;&lt;colgroup&gt;&lt;col style=&quot;width: 33.3009%\;&quot;&gt;
 &lt;col style=&quot;width: 33.3009%\;&quot;&gt;&lt;col style=&quot;width: 33.3009%\;&quot;&gt;&lt;/colgroup&gt;\
 n&lt;tbody&gt;\n&lt;tr&gt;\n&lt;td style=&quot;text-align: center\;&quot;&gt;&lt;img src=&quot;https://events.
 vtools.ieee.org/vtools_ui/media/display/fd594ed5-4ae6-4166-9a91-0a6c8da4b2
 8a&quot; alt=&quot;&quot; width=&quot;363&quot; height=&quot;204&quot;&gt;&lt;/td&gt;\n&lt;td style=&quot;text-align: center\;
 &quot;&gt;&lt;img src=&quot;https://events.vtools.ieee.org/vtools_ui/media/display/4fa2185
 e-58bd-4166-b79d-c2d006516612&quot; alt=&quot;&quot; width=&quot;355&quot; height=&quot;200&quot;&gt;&lt;/td&gt;\n&lt;td 
 style=&quot;text-align: center\;&quot;&gt;&lt;img src=&quot;https://events.vtools.ieee.org/vtoo
 ls_ui/media/display/776928ae-7cf3-49fc-9d54-0849e28a1adc&quot; alt=&quot;&quot; width=&quot;35
 8&quot; height=&quot;201&quot;&gt;&lt;/td&gt;\n&lt;/tr&gt;\n&lt;/tbody&gt;\n&lt;/table&gt;&lt;br /&gt;&lt;br /&gt;Agenda: &lt;br /&gt;
 &lt;p dir=&quot;ltr&quot;&gt;3:30 PM &amp;ndash\; 3:40 PM&lt;br&gt;Welcome Address and Introduction 
 of the Speaker&lt;/p&gt;\n&lt;p dir=&quot;ltr&quot;&gt;3:40 PM &amp;ndash\; 4:50 PM&lt;br&gt;Technical Tal
 k by Mr. Palash Khandale&lt;br&gt;Topic: ASIC Design Beyond Theory: Industry Exp
 erience and Practice&lt;/p&gt;\n&lt;p dir=&quot;ltr&quot;&gt;4:50 PM &amp;ndash\; 5:00 PM&lt;br&gt;Interac
 tive Q&amp;amp\;A Session&lt;/p&gt;\n&lt;p&gt;5:00 PM&lt;br&gt;Vote of Thanks and Felicitation&lt;/
 p&gt;
END:VEVENT
END:VCALENDAR