BEGIN:VCALENDAR
VERSION:2.0
PRODID:IEEE vTools.Events//EN
CALSCALE:GREGORIAN
BEGIN:VTIMEZONE
TZID:Asia/Kolkata
BEGIN:STANDARD
DTSTART:19451014T230000
TZOFFSETFROM:+0630
TZOFFSETTO:+0530
TZNAME:IST
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END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20260301T162222Z
UID:5758495A-111A-4623-9AC6-5FBFC7F74D43
DTSTART;TZID=Asia/Kolkata:20260317T150000
DTEND;TZID=Asia/Kolkata:20260319T220000
DESCRIPTION:Semiconductor Summit 2.0 is a three-day flagship technical even
 t organized by the EC Department\, CHARUSAT\, bringing together academia\,
  industry experts\, innovators\, and aspiring engineers to explore the evo
 lving semiconductor ecosystem.\n\nThe summit is designed to bridge the gap
  between theoretical learning and real-world semiconductor industry practi
 ces. It focuses on VLSI\, FPGA\, RTL Design\, Design Verification\, Embedd
 ed Systems\, and AI-powered chip development.\n\nThe event includes:\n\n
 • Expert-led panel discussions on Fabless Semiconductor Innovation (RTL 
 to ASIC/SoC Implementation)\n• Hands-on workshops on Industry-Ready RTL 
 Coding &amp; FPGA Implementation\n• Industry Insight Sessions comparing Embe
 dded Systems vs VLSI career paths\n• Deep-dive session on AI Powered VLS
 I – Transforming Engineers\n• Silicon Shark Tank – Industry-driven i
 dea pitching competition\n• Silent Silicon Gallery – Technical Poster 
 Presentations &amp; Live Demonstrations\n• Stall Visit: Wafer to Chip demons
 tration (Sand to Silicon journey)\n• The Silicon Jackpot – Treasure Hu
 nt &amp; FPGA Faceoff\n• Interactive Technical Engagement Activities &amp; Tech 
 Games\n\nWinning teams will receive internship opportunities and exciting 
 technical rewards. The summit emphasizes innovation\, skill-building\, pro
 blem-solving\, and industry readiness.\n\nThis event aims to empower stude
 nts to become next-generation semiconductor professionals and contribute t
 o India’s growing chip design ecosystem.\n\nCo-sponsored by: Charotar Un
 iversity of Science and Technology (CHARUSAT)\n\nAgenda: \n📅 DAY 1 – 
 Tuesday\, 17/03/2026\n\n09:30 AM – 10:30 AM\nWelcome of Guests &amp; Refresh
 ments – Reception and Networking\n\n10:30 AM – 10:40 AM\nInauguration 
 Ceremony – Formal Opening of the Summit\n\n10:50 AM – 11:30 AM\nInaugu
 ral Talk – Speaker: Sudhir Naik\n\n11:30 AM – 12:30 PM\nPanel Discussi
 on – “Fabless Startups and Fabless MSMEs: Accelerating Semiconductor G
 rowth”\nExperts: CEOs &amp; Directors from Leading Semiconductor Companies\n
 \n12:30 PM – 01:30 PM\nLunch Break &amp; Networking\n\n01:30 PM – 04:30 PM
 \nHands-on Workshop 1 – Good Coding Practices in Verilog: Writing Indust
 ry-Ready Self-Checking Testbenches\n(For Pre-Final &amp; Final Year Students)\
 n\nHands-on Workshop 2 – Getting Started with Verilog &amp; FPGA\n(For First
  Year / Fourth Semester Students)\n---------------------------------------
 ------------------------\n\n📅 DAY 2 – Wednesday\, 18/03/2026\n\n09:00
  AM – 09:30 AM\nRefreshments\n\n09:45 AM – 11:00 AM\nTechnical Session
  1 – “Embedded vs VLSI – What Should I Choose?”\nExpert: Nikul Sha
 h\, CEO – IndiSemic\n\n11:00 AM – 12:10 PM\nLunch Break &amp; Networking\n
 \n12:30 PM – 04:30 PM\nSilicon Shark Tank – Industry-Driven Idea Pitch
 ing Competition\n(Industry Sharks – To Be Announced)\n\nSilent Silicon I
 deas Gallery – Technical Poster &amp; Project Demonstrations\n\nStall Visit 
 – Wafer-to-Chip Demonstration by Monk9\n--------------------------------
 -------------------------------\n\n📅 DAY 3 – Thursday\, 19/03/2026\n\
 n09:00 AM – 09:30 AM\nRefreshments\n\n09:45 AM – 11:00 AM\nTechnical S
 ession 2 – “AI Powered VLSI – Shaping the NextGen Design Verificatio
 n Engineers”\nExpert: Kaushal Modi\, Associate Director – eInfochips\n
 \n11:00 AM – 12:00 PM\nLunch Break &amp; Networking\n\n12:10 PM – 03:30 PM
 \nThe Silicon Jackpot – Technical Treasure Hunt\nOrganized by VLSI Club\
 n\nInteractive Technical Engagement Activities – Problem-Solving Challen
 ges &amp; Tech Games\nOrganized by VLSI Club\n\n03:30 PM – 04:30 PM\nAwards 
 &amp; Closing Ceremony – Prize Distribution &amp; Valedictory\n\nRoom: -\, Bldg:
  A6\, Department of Electronics and Communication\, Charotar University of
  Science and Technology (CHARUSAT)\, CSPIT Campus\, Off Nadiad-Petlad High
 way\, Changa\, Anand\, Gujarat\, India\, 388421
LOCATION:Room: -\, Bldg: A6\, Department of Electronics and Communication\,
  Charotar University of Science and Technology (CHARUSAT)\, CSPIT Campus\,
  Off Nadiad-Petlad Highway\, Changa\, Anand\, Gujarat\, India\, 388421
ORGANIZER:dhruvrupapara@ieee.org
SEQUENCE:13
SUMMARY:Semiconductor Summit 2.0 – Architecting the Future of Chips
URL;VALUE=URI:https://events.vtools.ieee.org/m/543844
X-ALT-DESC:Description: &lt;br /&gt;&lt;p data-start=&quot;656&quot; data-end=&quot;892&quot;&gt;Semiconduc
 tor Summit 2.0 is a three-day flagship technical event organized by the EC
  Department\, CHARUSAT\, bringing together academia\, industry experts\, i
 nnovators\, and aspiring engineers to explore the evolving semiconductor e
 cosystem.&lt;/p&gt;\n&lt;p data-start=&quot;894&quot; data-end=&quot;1122&quot;&gt;The summit is designed 
 to bridge the gap between theoretical learning and real-world semiconducto
 r industry practices. It focuses on VLSI\, FPGA\, RTL Design\, Design Veri
 fication\, Embedded Systems\, and AI-powered chip development.&lt;/p&gt;\n&lt;p dat
 a-start=&quot;1124&quot; data-end=&quot;1143&quot;&gt;The event includes:&lt;/p&gt;\n&lt;p data-start=&quot;114
 5&quot; data-end=&quot;1800&quot;&gt;&amp;bull\; Expert-led panel discussions on Fabless Semicon
 ductor Innovation (RTL to ASIC/SoC Implementation)&lt;br data-start=&quot;1244&quot; da
 ta-end=&quot;1247&quot;&gt;&amp;bull\; Hands-on workshops on Industry-Ready RTL Coding &amp;amp
 \; FPGA Implementation&lt;br data-start=&quot;1318&quot; data-end=&quot;1321&quot;&gt;&amp;bull\; Indust
 ry Insight Sessions comparing Embedded Systems vs VLSI career paths&lt;br dat
 a-start=&quot;1396&quot; data-end=&quot;1399&quot;&gt;&amp;bull\; Deep-dive session on AI Powered VLS
 I &amp;ndash\; Transforming Engineers&lt;br data-start=&quot;1462&quot; data-end=&quot;1465&quot;&gt;&amp;bu
 ll\; Silicon Shark Tank &amp;ndash\; Industry-driven idea pitching competition
 &lt;br data-start=&quot;1529&quot; data-end=&quot;1532&quot;&gt;&amp;bull\; Silent Silicon Gallery &amp;ndas
 h\; Technical Poster Presentations &amp;amp\; Live Demonstrations&lt;br data-star
 t=&quot;1611&quot; data-end=&quot;1614&quot;&gt;&amp;bull\; Stall Visit: Wafer to Chip demonstration 
 (Sand to Silicon journey)&lt;br data-start=&quot;1682&quot; data-end=&quot;1685&quot;&gt;&amp;bull\; The
  Silicon Jackpot &amp;ndash\; Treasure Hunt &amp;amp\; FPGA Faceoff&lt;br data-start=
 &quot;1737&quot; data-end=&quot;1740&quot;&gt;&amp;bull\; Interactive Technical Engagement Activities
  &amp;amp\; Tech Games&lt;/p&gt;\n&lt;p data-start=&quot;1802&quot; data-end=&quot;1976&quot;&gt;Winning teams
  will receive internship opportunities and exciting technical rewards. The
  summit emphasizes innovation\, skill-building\, problem-solving\, and ind
 ustry readiness.&lt;/p&gt;\n&lt;p data-start=&quot;1978&quot; data-end=&quot;2124&quot;&gt;This event aims
  to empower students to become next-generation semiconductor professionals
  and contribute to India&amp;rsquo\;s growing chip design ecosystem.&lt;/p&gt;\n&lt;p d
 ata-start=&quot;1978&quot; data-end=&quot;2124&quot;&gt;&amp;nbsp\;&lt;/p&gt;\n&lt;p data-start=&quot;1978&quot; data-en
 d=&quot;2124&quot;&gt;&lt;img src=&quot;https://events.vtools.ieee.org/vtools_ui/media/display/
 01fcc46c-d6c0-4aa3-917f-0f3a6debee80&quot; width=&quot;994&quot; height=&quot;1242&quot;&gt;&lt;/p&gt;&lt;br /&gt;
 &lt;br /&gt;Agenda: &lt;br /&gt;&lt;h2 data-start=&quot;235&quot; data-end=&quot;268&quot;&gt;📅 DAY 1 &amp;ndash\
 ; Tuesday\, 17/03/2026&lt;/h2&gt;\n&lt;p data-start=&quot;270&quot; data-end=&quot;357&quot;&gt;&lt;strong da
 ta-start=&quot;270&quot; data-end=&quot;293&quot;&gt;09:30 AM &amp;ndash\; 10:30 AM&lt;/strong&gt;&lt;br data-
 start=&quot;293&quot; data-end=&quot;296&quot;&gt;Welcome of Guests &amp;amp\; Refreshments &amp;ndash\; 
 Reception and Networking&lt;/p&gt;\n&lt;p data-start=&quot;359&quot; data-end=&quot;439&quot;&gt;&lt;strong d
 ata-start=&quot;359&quot; data-end=&quot;382&quot;&gt;10:30 AM &amp;ndash\; 10:40 AM&lt;/strong&gt;&lt;br data
 -start=&quot;382&quot; data-end=&quot;385&quot;&gt;Inauguration Ceremony &amp;ndash\; Formal Opening 
 of the Summit&lt;/p&gt;\n&lt;p data-start=&quot;441&quot; data-end=&quot;506&quot;&gt;&lt;strong data-start=&quot;
 441&quot; data-end=&quot;464&quot;&gt;10:50 AM &amp;ndash\; 11:30 AM&lt;/strong&gt;&lt;br data-start=&quot;464
 &quot; data-end=&quot;467&quot;&gt;Inaugural Talk &amp;ndash\; Speaker: Sudhir Naik&lt;/p&gt;\n&lt;p data
 -start=&quot;508&quot; data-end=&quot;691&quot;&gt;&lt;strong data-start=&quot;508&quot; data-end=&quot;531&quot;&gt;11:30 
 AM &amp;ndash\; 12:30 PM&lt;/strong&gt;&lt;br data-start=&quot;531&quot; data-end=&quot;534&quot;&gt;Panel Dis
 cussion &amp;ndash\; &amp;ldquo\;Fabless Startups and Fabless MSMEs: Accelerating 
 Semiconductor Growth&amp;rdquo\;&lt;br data-start=&quot;624&quot; data-end=&quot;627&quot;&gt;Experts: C
 EOs &amp;amp\; Directors from Leading Semiconductor Companies&lt;/p&gt;\n&lt;p data-sta
 rt=&quot;693&quot; data-end=&quot;745&quot;&gt;&lt;strong data-start=&quot;693&quot; data-end=&quot;716&quot;&gt;12:30 PM &amp;
 ndash\; 01:30 PM&lt;/strong&gt;&lt;br data-start=&quot;716&quot; data-end=&quot;719&quot;&gt;Lunch Break &amp;
 amp\; Networking&lt;/p&gt;\n&lt;p data-start=&quot;747&quot; data-end=&quot;919&quot;&gt;&lt;strong data-star
 t=&quot;747&quot; data-end=&quot;770&quot;&gt;01:30 PM &amp;ndash\; 04:30 PM&lt;/strong&gt;&lt;br data-start=&quot;
 770&quot; data-end=&quot;773&quot;&gt;Hands-on Workshop 1 &amp;ndash\; Good Coding Practices in 
 Verilog: Writing Industry-Ready Self-Checking Testbenches&lt;br data-start=&quot;8
 77&quot; data-end=&quot;880&quot;&gt;(For Pre-Final &amp;amp\; Final Year Students)&lt;/p&gt;\n&lt;p data
 -start=&quot;921&quot; data-end=&quot;1026&quot;&gt;Hands-on Workshop 2 &amp;ndash\; Getting Started 
 with Verilog &amp;amp\; FPGA&lt;br data-start=&quot;978&quot; data-end=&quot;981&quot;&gt;(For First Yea
 r / Fourth Semester Students)&lt;/p&gt;\n&lt;hr data-start=&quot;1028&quot; data-end=&quot;1031&quot;&gt;\
 n&lt;h2 data-start=&quot;1033&quot; data-end=&quot;1068&quot;&gt;📅 DAY 2 &amp;ndash\; Wednesday\, 18/
 03/2026&lt;/h2&gt;\n&lt;p data-start=&quot;1070&quot; data-end=&quot;1110&quot;&gt;&lt;strong data-start=&quot;107
 0&quot; data-end=&quot;1093&quot;&gt;09:00 AM &amp;ndash\; 09:30 AM&lt;/strong&gt;&lt;br data-start=&quot;1093
 &quot; data-end=&quot;1096&quot;&gt;Refreshments&lt;/p&gt;\n&lt;p data-start=&quot;1112&quot; data-end=&quot;1242&quot;&gt;&lt;
 strong data-start=&quot;1112&quot; data-end=&quot;1135&quot;&gt;09:45 AM &amp;ndash\; 11:00 AM&lt;/stron
 g&gt;&lt;br data-start=&quot;1135&quot; data-end=&quot;1138&quot;&gt;Technical Session 1 &amp;ndash\; &amp;ldqu
 o\;Embedded vs VLSI &amp;ndash\; What Should I Choose?&amp;rdquo\;&lt;br data-start=&quot;
 1202&quot; data-end=&quot;1205&quot;&gt;Expert: Nikul Shah\, CEO &amp;ndash\; IndiSemic&lt;/p&gt;\n&lt;p 
 data-start=&quot;1244&quot; data-end=&quot;1296&quot;&gt;&lt;strong data-start=&quot;1244&quot; data-end=&quot;1267
 &quot;&gt;11:00 AM &amp;ndash\; 12:10 PM&lt;/strong&gt;&lt;br data-start=&quot;1267&quot; data-end=&quot;1270&quot;
 &gt;Lunch Break &amp;amp\; Networking&lt;/p&gt;\n&lt;p data-start=&quot;1298&quot; data-end=&quot;1426&quot;&gt;&lt;
 strong data-start=&quot;1298&quot; data-end=&quot;1321&quot;&gt;12:30 PM &amp;ndash\; 04:30 PM&lt;/stron
 g&gt;&lt;br data-start=&quot;1321&quot; data-end=&quot;1324&quot;&gt;Silicon Shark Tank &amp;ndash\; Indust
 ry-Driven Idea Pitching Competition&lt;br data-start=&quot;1386&quot; data-end=&quot;1389&quot;&gt;(
 Industry Sharks &amp;ndash\; To Be Announced)&lt;/p&gt;\n&lt;p data-start=&quot;1428&quot; data-e
 nd=&quot;1502&quot;&gt;Silent Silicon Ideas Gallery &amp;ndash\; Technical Poster &amp;amp\; Pr
 oject Demonstrations&lt;/p&gt;\n&lt;p data-start=&quot;1504&quot; data-end=&quot;1556&quot;&gt;Stall Visit
  &amp;ndash\; Wafer-to-Chip Demonstration by Monk9&lt;/p&gt;\n&lt;hr data-start=&quot;1558&quot; 
 data-end=&quot;1561&quot;&gt;\n&lt;h2 data-start=&quot;1563&quot; data-end=&quot;1597&quot;&gt;📅 DAY 3 &amp;ndash\
 ; Thursday\, 19/03/2026&lt;/h2&gt;\n&lt;p data-start=&quot;1599&quot; data-end=&quot;1639&quot;&gt;&lt;strong
  data-start=&quot;1599&quot; data-end=&quot;1622&quot;&gt;09:00 AM &amp;ndash\; 09:30 AM&lt;/strong&gt;&lt;br 
 data-start=&quot;1622&quot; data-end=&quot;1625&quot;&gt;Refreshments&lt;/p&gt;\n&lt;p data-start=&quot;1641&quot; d
 ata-end=&quot;1816&quot;&gt;&lt;strong data-start=&quot;1641&quot; data-end=&quot;1664&quot;&gt;09:45 AM &amp;ndash\;
  11:00 AM&lt;/strong&gt;&lt;br data-start=&quot;1664&quot; data-end=&quot;1667&quot;&gt;Technical Session 
 2 &amp;ndash\; &amp;ldquo\;AI Powered VLSI &amp;ndash\; Shaping the NextGen Design Ver
 ification Engineers&amp;rdquo\;&lt;br data-start=&quot;1758&quot; data-end=&quot;1761&quot;&gt;Expert: K
 aushal Modi\, Associate Director &amp;ndash\; eInfochips&lt;/p&gt;\n&lt;p data-start=&quot;1
 818&quot; data-end=&quot;1870&quot;&gt;&lt;strong data-start=&quot;1818&quot; data-end=&quot;1841&quot;&gt;11:00 AM &amp;n
 dash\; 12:00 PM&lt;/strong&gt;&lt;br data-start=&quot;1841&quot; data-end=&quot;1844&quot;&gt;Lunch Break 
 &amp;amp\; Networking&lt;/p&gt;\n&lt;p data-start=&quot;1872&quot; data-end=&quot;1970&quot;&gt;&lt;strong data-s
 tart=&quot;1872&quot; data-end=&quot;1895&quot;&gt;12:10 PM &amp;ndash\; 03:30 PM&lt;/strong&gt;&lt;br data-st
 art=&quot;1895&quot; data-end=&quot;1898&quot;&gt;The Silicon Jackpot &amp;ndash\; Technical Treasure
  Hunt&lt;br data-start=&quot;1943&quot; data-end=&quot;1946&quot;&gt;Organized by VLSI Club&lt;/p&gt;\n&lt;p 
 data-start=&quot;1972&quot; data-end=&quot;2084&quot;&gt;Interactive Technical Engagement Activit
 ies &amp;ndash\; Problem-Solving Challenges &amp;amp\; Tech Games&lt;br data-start=&quot;2
 057&quot; data-end=&quot;2060&quot;&gt;Organized by VLSI Club&lt;/p&gt;\n&lt;p data-start=&quot;2086&quot; data
 -end=&quot;2174&quot;&gt;&lt;strong data-start=&quot;2086&quot; data-end=&quot;2109&quot;&gt;03:30 PM &amp;ndash\; 04
 :30 PM&lt;/strong&gt;&lt;br data-start=&quot;2109&quot; data-end=&quot;2112&quot;&gt;Awards &amp;amp\; Closing
  Ceremony &amp;ndash\; Prize Distribution &amp;amp\; Valedictory&lt;/p&gt;
END:VEVENT
END:VCALENDAR