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DTSTART:19451014T230000
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TZOFFSETTO:+0530
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BEGIN:VEVENT
DTSTAMP:20260312T084738Z
UID:10FC0714-9540-468B-82E1-A1ADA1A95009
DTSTART;TZID=Asia/Kolkata:20250908T090000
DTEND;TZID=Asia/Kolkata:20250913T160000
DESCRIPTION:Workshop on Front-End Design Verification\n\nThe Front-End Desi
 gn Verification workshop is a specialized training session organized by th
 e Department of Electrical and Computer Engineering (ECE) in association w
 ith the IEEE NEC Student Branch at Narasaraopeta Engineering College (NEC)
 . This workshop will be held from 8th to 13th September 2025 and will be c
 onducted by Mr. Srikanth Bandla\, an expert from TRIKO Semiconductor Solut
 ions\, Narasaraopet.\n\nThis workshop aims to provide participants with in
 -depth knowledge and hands-on experience in front-end design verification\
 , an essential process in the development of digital systems. Front-end de
 sign verification ensures that the digital design of a chip or system func
 tions as intended before moving on to the next stages of production. Parti
 cipants will learn about various verification tools and methodologies\, in
 cluding simulation\, modeling\, and debugging techniques. The workshop wil
 l also cover the latest industry practices in semiconductor design\, offer
 ing a comprehensive understanding of the front-end verification lifecycle.
 \n\nBy attending this workshop\, students will gain practical insights int
 o the semiconductor design process\, an area that is highly relevant to in
 dustries like VLSI (Very-Large-Scale Integration)\, electronics\, and comp
 uter engineering. This workshop is ideal for students looking to enhance t
 heir technical skills and pursue careers in the semiconductor and electron
 ics fields.\n\nSpeaker(s): SRIKANTH\n\nAgenda: \n-\nIntroduction and Welco
 me\n\n-\nIntroduction to the workshop and its objectives.\n\n-\nOverview o
 f the significance of front-end design verification in semiconductor and d
 igital system development.\n\n-\nIntroduction to the resource person\, Mr.
  Srikanth Bandla from TRIKO Semiconductor Solutions.\n\n-\nFundamentals of
  Front-End Design Verification\n\n-\nIntroduction to front-end design in t
 he context of semiconductor systems.\n\n-\nOverview of the design verifica
 tion process and its importance.\n\n-\nKey concepts in design verification
 : simulation\, modeling\, and debugging.\n\n-\nTools and Techniques for De
 sign Verification\n\n-\nIntroduction to industry-standard verification too
 ls.\n\n-\nExplanation of simulation methodologies and their application in
  front-end verification.\n\n-\nHands-on training on the usage of verificat
 ion tools.\n\n-\nVerification Methodologies\n\n-\nOverview of verification
  methodologies like UVM (Universal Verification Methodology) and SystemVer
 ilog.\n\n-\nBest practices in verification and how to implement them effec
 tively.\n\n-\nPractical Session: Hands-On Verification\n\n-\nReal-time exa
 mples and practical exercises for participants.\n\n-\nStep-by-step guidanc
 e on verifying digital designs.\n\n-\nTroubleshooting common issues during
  the verification process.\n\n-\nChallenges in Front-End Design Verificati
 on\n\n-\nIdentifying common challenges faced in the verification process.\
 n\n-\nDiscussion of potential solutions to overcome verification issues.\n
 \n-\nEmerging Trends in Semiconductor Design\n\n-\nIntroduction to the lat
 est trends and advancements in semiconductor design verification.\n\n-\nDi
 scussion on the future of front-end verification techniques and tools.\n\n
 -\nQ&amp;A Session\n\n-\nOpen floor for participants to ask questions and disc
 uss specific topics related to front-end design verification.\n\n-\nClosin
 g Remarks\n\n-\nSummary of key takeaways from the workshop.\n\n-\nAcknowle
 dgments to the guest speaker and participants.\n\n-\nDetails for further l
 earning resources and career opportunities in semiconductor and verificati
 on fields.\n\nBldg: BLOCK-3\, NARSARAOPETA ENGINEERING COLLEGE\, NARSARAOP
 ET\, Andhra Pradesh\, India\, 522601
LOCATION:Bldg: BLOCK-3\, NARSARAOPETA ENGINEERING COLLEGE\, NARSARAOPET\, A
 ndhra Pradesh\, India\, 522601
ORGANIZER:raju.kolluri@gmail.com
SEQUENCE:18
SUMMARY:FRONT-END DESIGN VERIFICATION
URL;VALUE=URI:https://events.vtools.ieee.org/m/546782
X-ALT-DESC:Description: &lt;br /&gt;&lt;h3 data-section-id=&quot;12sp7ka&quot; data-start=&quot;0&quot; 
 data-end=&quot;49&quot;&gt;&lt;strong data-start=&quot;4&quot; data-end=&quot;49&quot;&gt;Workshop on Front-End D
 esign Verification&lt;/strong&gt;&lt;/h3&gt;\n&lt;p data-start=&quot;51&quot; data-end=&quot;481&quot;&gt;The &lt;s
 trong data-start=&quot;55&quot; data-end=&quot;88&quot;&gt;Front-End Design Verification&lt;/strong&gt;
  workshop is a specialized training session organized by the Department of
  Electrical and Computer Engineering (ECE) in association with the &lt;strong
  data-start=&quot;229&quot; data-end=&quot;256&quot;&gt;IEEE NEC Student Branch&lt;/strong&gt; at &lt;stro
 ng data-start=&quot;260&quot; data-end=&quot;303&quot;&gt;Narasaraopeta Engineering College (NEC)
 &lt;/strong&gt;. This workshop will be held from &lt;strong data-start=&quot;337&quot; data-e
 nd=&quot;367&quot;&gt;8th to 13th September 2025&lt;/strong&gt; and will be conducted by &lt;str
 ong data-start=&quot;393&quot; data-end=&quot;416&quot;&gt;Mr. Srikanth Bandla&lt;/strong&gt;\, an expe
 rt from &lt;strong data-start=&quot;433&quot; data-end=&quot;466&quot;&gt;TRIKO Semiconductor Soluti
 ons&lt;/strong&gt;\, Narasaraopet.&lt;/p&gt;\n&lt;p data-start=&quot;483&quot; data-end=&quot;1120&quot;&gt;This
  workshop aims to provide participants with in-depth knowledge and hands-o
 n experience in front-end design verification\, an essential process in th
 e development of digital systems. Front-end design verification ensures th
 at the digital design of a chip or system functions as intended before mov
 ing on to the next stages of production. Participants will learn about var
 ious verification tools and methodologies\, including simulation\, modelin
 g\, and debugging techniques. The workshop will also cover the latest indu
 stry practices in semiconductor design\, offering a comprehensive understa
 nding of the front-end verification lifecycle.&lt;/p&gt;\n&lt;p data-start=&quot;1122&quot; d
 ata-end=&quot;1495&quot;&gt;By attending this workshop\, students will gain practical i
 nsights into the semiconductor design process\, an area that is highly rel
 evant to industries like VLSI (Very-Large-Scale Integration)\, electronics
 \, and computer engineering. This workshop is ideal for students looking t
 o enhance their technical skills and pursue careers in the semiconductor a
 nd electronics fields.&lt;/p&gt;&lt;br /&gt;&lt;br /&gt;Agenda: &lt;br /&gt;&lt;ul&gt;\n&lt;li data-section
 -id=&quot;1vmtryq&quot; data-start=&quot;64&quot; data-end=&quot;363&quot;&gt;\n&lt;p data-start=&quot;67&quot; data-end
 =&quot;95&quot;&gt;&lt;strong data-start=&quot;67&quot; data-end=&quot;95&quot;&gt;Introduction and Welcome&lt;/stro
 ng&gt;&lt;/p&gt;\n&lt;ul data-start=&quot;99&quot; data-end=&quot;363&quot;&gt;\n&lt;li data-section-id=&quot;1s8vvlk
 &quot; data-start=&quot;99&quot; data-end=&quot;149&quot;&gt;\n&lt;p data-start=&quot;101&quot; data-end=&quot;149&quot;&gt;Intr
 oduction to the workshop and its objectives.&lt;/p&gt;\n&lt;/li&gt;\n&lt;li data-section-
 id=&quot;19n8uqo&quot; data-start=&quot;153&quot; data-end=&quot;265&quot;&gt;\n&lt;p data-start=&quot;155&quot; data-en
 d=&quot;265&quot;&gt;Overview of the significance of front-end design verification in s
 emiconductor and digital system development.&lt;/p&gt;\n&lt;/li&gt;\n&lt;li data-section-
 id=&quot;621h5a&quot; data-start=&quot;269&quot; data-end=&quot;363&quot;&gt;\n&lt;p data-start=&quot;271&quot; data-end
 =&quot;363&quot;&gt;Introduction to the resource person\, Mr. Srikanth Bandla from TRIK
 O Semiconductor Solutions.&lt;/p&gt;\n&lt;/li&gt;\n&lt;/ul&gt;\n&lt;/li&gt;\n&lt;li data-section-id=&quot;
 rf3hgr&quot; data-start=&quot;365&quot; data-end=&quot;644&quot;&gt;\n&lt;p data-start=&quot;368&quot; data-end=&quot;41
 7&quot;&gt;&lt;strong data-start=&quot;368&quot; data-end=&quot;417&quot;&gt;Fundamentals of Front-End Desig
 n Verification&lt;/strong&gt;&lt;/p&gt;\n&lt;ul data-start=&quot;421&quot; data-end=&quot;644&quot;&gt;\n&lt;li dat
 a-section-id=&quot;v8yvmh&quot; data-start=&quot;421&quot; data-end=&quot;496&quot;&gt;\n&lt;p data-start=&quot;423
 &quot; data-end=&quot;496&quot;&gt;Introduction to front-end design in the context of semico
 nductor systems.&lt;/p&gt;\n&lt;/li&gt;\n&lt;li data-section-id=&quot;klq7j8&quot; data-start=&quot;500&quot;
  data-end=&quot;565&quot;&gt;\n&lt;p data-start=&quot;502&quot; data-end=&quot;565&quot;&gt;Overview of the desig
 n verification process and its importance.&lt;/p&gt;\n&lt;/li&gt;\n&lt;li data-section-id
 =&quot;1n1adg5&quot; data-start=&quot;569&quot; data-end=&quot;644&quot;&gt;\n&lt;p data-start=&quot;571&quot; data-end=
 &quot;644&quot;&gt;Key concepts in design verification: simulation\, modeling\, and deb
 ugging.&lt;/p&gt;\n&lt;/li&gt;\n&lt;/ul&gt;\n&lt;/li&gt;\n&lt;li data-section-id=&quot;1po0by5&quot; data-start
 =&quot;646&quot; data-end=&quot;909&quot;&gt;\n&lt;p data-start=&quot;649&quot; data-end=&quot;697&quot;&gt;&lt;strong data-st
 art=&quot;649&quot; data-end=&quot;697&quot;&gt;Tools and Techniques for Design Verification&lt;/str
 ong&gt;&lt;/p&gt;\n&lt;ul data-start=&quot;701&quot; data-end=&quot;909&quot;&gt;\n&lt;li data-section-id=&quot;1s05i
 9v&quot; data-start=&quot;701&quot; data-end=&quot;756&quot;&gt;\n&lt;p data-start=&quot;703&quot; data-end=&quot;756&quot;&gt;I
 ntroduction to industry-standard verification tools.&lt;/p&gt;\n&lt;/li&gt;\n&lt;li data-
 section-id=&quot;1qzoxu2&quot; data-start=&quot;760&quot; data-end=&quot;850&quot;&gt;\n&lt;p data-start=&quot;762&quot;
  data-end=&quot;850&quot;&gt;Explanation of simulation methodologies and their applicat
 ion in front-end verification.&lt;/p&gt;\n&lt;/li&gt;\n&lt;li data-section-id=&quot;e01iqk&quot; da
 ta-start=&quot;854&quot; data-end=&quot;909&quot;&gt;\n&lt;p data-start=&quot;856&quot; data-end=&quot;909&quot;&gt;Hands-o
 n training on the usage of verification tools.&lt;/p&gt;\n&lt;/li&gt;\n&lt;/ul&gt;\n&lt;/li&gt;\n&lt;
 li data-section-id=&quot;159j3q7&quot; data-start=&quot;911&quot; data-end=&quot;1136&quot;&gt;\n&lt;p data-st
 art=&quot;914&quot; data-end=&quot;944&quot;&gt;&lt;strong data-start=&quot;914&quot; data-end=&quot;944&quot;&gt;Verificat
 ion Methodologies&lt;/strong&gt;&lt;/p&gt;\n&lt;ul data-start=&quot;948&quot; data-end=&quot;1136&quot;&gt;\n&lt;li
  data-section-id=&quot;15i40w1&quot; data-start=&quot;948&quot; data-end=&quot;1061&quot;&gt;\n&lt;p data-star
 t=&quot;950&quot; data-end=&quot;1061&quot;&gt;Overview of verification methodologies like &lt;stron
 g data-start=&quot;994&quot; data-end=&quot;1038&quot;&gt;UVM (Universal Verification Methodology
 )&lt;/strong&gt; and &lt;strong data-start=&quot;1043&quot; data-end=&quot;1060&quot;&gt;SystemVerilog&lt;/st
 rong&gt;.&lt;/p&gt;\n&lt;/li&gt;\n&lt;li data-section-id=&quot;18cyrsj&quot; data-start=&quot;1065&quot; data-en
 d=&quot;1136&quot;&gt;\n&lt;p data-start=&quot;1067&quot; data-end=&quot;1136&quot;&gt;Best practices in verifica
 tion and how to implement them effectively.&lt;/p&gt;\n&lt;/li&gt;\n&lt;/ul&gt;\n&lt;/li&gt;\n&lt;li 
 data-section-id=&quot;whohwh&quot; data-start=&quot;1138&quot; data-end=&quot;1376&quot;&gt;\n&lt;p data-start
 =&quot;1141&quot; data-end=&quot;1185&quot;&gt;&lt;strong data-start=&quot;1141&quot; data-end=&quot;1185&quot;&gt;Practica
 l Session: Hands-On Verification&lt;/strong&gt;&lt;/p&gt;\n&lt;ul data-start=&quot;1189&quot; data-
 end=&quot;1376&quot;&gt;\n&lt;li data-section-id=&quot;bw8qfp&quot; data-start=&quot;1189&quot; data-end=&quot;1251
 &quot;&gt;\n&lt;p data-start=&quot;1191&quot; data-end=&quot;1251&quot;&gt;Real-time examples and practical 
 exercises for participants.&lt;/p&gt;\n&lt;/li&gt;\n&lt;li data-section-id=&quot;1gx7ex2&quot; data
 -start=&quot;1255&quot; data-end=&quot;1308&quot;&gt;\n&lt;p data-start=&quot;1257&quot; data-end=&quot;1308&quot;&gt;Step-
 by-step guidance on verifying digital designs.&lt;/p&gt;\n&lt;/li&gt;\n&lt;li data-sectio
 n-id=&quot;zu9fn5&quot; data-start=&quot;1312&quot; data-end=&quot;1376&quot;&gt;\n&lt;p data-start=&quot;1314&quot; dat
 a-end=&quot;1376&quot;&gt;Troubleshooting common issues during the verification process
 .&lt;/p&gt;\n&lt;/li&gt;\n&lt;/ul&gt;\n&lt;/li&gt;\n&lt;li data-section-id=&quot;4p2twj&quot; data-start=&quot;1378&quot;
  data-end=&quot;1570&quot;&gt;\n&lt;p data-start=&quot;1381&quot; data-end=&quot;1428&quot;&gt;&lt;strong data-start
 =&quot;1381&quot; data-end=&quot;1428&quot;&gt;Challenges in Front-End Design Verification&lt;/stron
 g&gt;&lt;/p&gt;\n&lt;ul data-start=&quot;1432&quot; data-end=&quot;1570&quot;&gt;\n&lt;li data-section-id=&quot;up9ah
 i&quot; data-start=&quot;1432&quot; data-end=&quot;1498&quot;&gt;\n&lt;p data-start=&quot;1434&quot; data-end=&quot;1498
 &quot;&gt;Identifying common challenges faced in the verification process.&lt;/p&gt;\n&lt;/
 li&gt;\n&lt;li data-section-id=&quot;1dkpdiv&quot; data-start=&quot;1502&quot; data-end=&quot;1570&quot;&gt;\n&lt;p 
 data-start=&quot;1504&quot; data-end=&quot;1570&quot;&gt;Discussion of potential solutions to ove
 rcome verification issues.&lt;/p&gt;\n&lt;/li&gt;\n&lt;/ul&gt;\n&lt;/li&gt;\n&lt;li data-section-id=&quot;
 r82ead&quot; data-start=&quot;1572&quot; data-end=&quot;1790&quot;&gt;\n&lt;p data-start=&quot;1575&quot; data-end=
 &quot;1618&quot;&gt;&lt;strong data-start=&quot;1575&quot; data-end=&quot;1618&quot;&gt;Emerging Trends in Semico
 nductor Design&lt;/strong&gt;&lt;/p&gt;\n&lt;ul data-start=&quot;1622&quot; data-end=&quot;1790&quot;&gt;\n&lt;li d
 ata-section-id=&quot;1sm8ooi&quot; data-start=&quot;1622&quot; data-end=&quot;1712&quot;&gt;\n&lt;p data-start
 =&quot;1624&quot; data-end=&quot;1712&quot;&gt;Introduction to the latest trends and advancements
  in semiconductor design verification.&lt;/p&gt;\n&lt;/li&gt;\n&lt;li data-section-id=&quot;ru
 5ocn&quot; data-start=&quot;1716&quot; data-end=&quot;1790&quot;&gt;\n&lt;p data-start=&quot;1718&quot; data-end=&quot;1
 790&quot;&gt;Discussion on the future of front-end verification techniques and too
 ls.&lt;/p&gt;\n&lt;/li&gt;\n&lt;/ul&gt;\n&lt;/li&gt;\n&lt;li data-section-id=&quot;t2z14r&quot; data-start=&quot;179
 2&quot; data-end=&quot;1930&quot;&gt;\n&lt;p data-start=&quot;1795&quot; data-end=&quot;1810&quot;&gt;&lt;strong data-sta
 rt=&quot;1795&quot; data-end=&quot;1810&quot;&gt;Q&amp;amp\;A Session&lt;/strong&gt;&lt;/p&gt;\n&lt;ul data-start=&quot;1
 814&quot; data-end=&quot;1930&quot;&gt;\n&lt;li data-section-id=&quot;9vv0zz&quot; data-start=&quot;1814&quot; data
 -end=&quot;1930&quot;&gt;\n&lt;p data-start=&quot;1816&quot; data-end=&quot;1930&quot;&gt;Open floor for particip
 ants to ask questions and discuss specific topics related to front-end des
 ign verification.&lt;/p&gt;\n&lt;/li&gt;\n&lt;/ul&gt;\n&lt;/li&gt;\n&lt;li data-section-id=&quot;8o4zsq&quot; d
 ata-start=&quot;1932&quot; data-end=&quot;2174&quot; data-is-last-node=&quot;&quot;&gt;\n&lt;p data-start=&quot;193
 5&quot; data-end=&quot;1954&quot;&gt;&lt;strong data-start=&quot;1935&quot; data-end=&quot;1954&quot;&gt;Closing Remar
 ks&lt;/strong&gt;&lt;/p&gt;\n&lt;ul data-start=&quot;1958&quot; data-end=&quot;2174&quot; data-is-last-node=&quot;
 &quot;&gt;\n&lt;li data-section-id=&quot;9e113s&quot; data-start=&quot;1958&quot; data-end=&quot;2003&quot;&gt;\n&lt;p da
 ta-start=&quot;1960&quot; data-end=&quot;2003&quot;&gt;Summary of key takeaways from the workshop
 .&lt;/p&gt;\n&lt;/li&gt;\n&lt;li data-section-id=&quot;1dism58&quot; data-start=&quot;2007&quot; data-end=&quot;20
 63&quot;&gt;\n&lt;p data-start=&quot;2009&quot; data-end=&quot;2063&quot;&gt;Acknowledgments to the guest sp
 eaker and participants.&lt;/p&gt;\n&lt;/li&gt;\n&lt;li data-section-id=&quot;632zmp&quot; data-star
 t=&quot;2067&quot; data-end=&quot;2174&quot; data-is-last-node=&quot;&quot;&gt;\n&lt;p data-start=&quot;2069&quot; data-
 end=&quot;2174&quot; data-is-last-node=&quot;&quot;&gt;Details for further learning resources and
  career opportunities in semiconductor and verification fields.&lt;/p&gt;\n&lt;/li&gt;
 \n&lt;/ul&gt;\n&lt;/li&gt;\n&lt;/ul&gt;
END:VEVENT
END:VCALENDAR