BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:Europe/Warsaw BEGIN:DAYLIGHT DTSTART:20260329T030000 TZOFFSETFROM:+0100 TZOFFSETTO:+0200 RRULE:FREQ=YEARLY;BYDAY=-1SU;BYMONTH=3 TZNAME:CEST END:DAYLIGHT BEGIN:STANDARD DTSTART:20251026T020000 TZOFFSETFROM:+0200 TZOFFSETTO:+0100 RRULE:FREQ=YEARLY;BYDAY=-1SU;BYMONTH=10 TZNAME:CET END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20260319T075234Z UID:E5BE20D2-F5EA-4B42-8AE3-8574F05494AD DTSTART;TZID=Europe/Warsaw:20260317T163000 DTEND;TZID=Europe/Warsaw:20260317T180000 DESCRIPTION:Abstract: The past two decades has seen proliferation of all-di gital phase-locked loops (ADPLL) for RF and high-performance frequency syn thesis due to their clear benefits of flexibility\, reconfigurability\, tr ansfer function precision\, settling speed\, frequency modulation capabili ty\, and amenability to integration with digital baseband and application processors. When implemented in nanoscale CMOS\, the ADPLL also exhibits a dvantages of better performance\, lower power consumption\, lower area and cost over the traditional analog-intensive charge-pump PLL. In a typical ADPLL\, a traditional VCO got directly replaced by a digitally controlled oscillator (DCO) for generating an output variable clock\, a traditional p hase/frequency detector and a charge pump got replaced by a time-to-digita l converter (TDC) for detecting phase departures of the variable clock ver sus the frequency reference (FREF) clock\, and an analog loop RC filter go t replaced with a digital loop filter. The conversion gains of the DCO and TDC circuits are readily estimated and compensated using “free” but p owerful digital logic.\n\nThe first three talks covered the fundamentals o f ADPLL\, its loop response and gear-shifting techniques. This fourth talk will cover direct frequency modulation capabilities of ADPLL and DCO fund amentals.\n\nRoom: 224\, Bldg: C2\, AGH University\, Kraków\, Malopolskie \, Poland\, Virtual: https://events.vtools.ieee.org/m/548979 LOCATION:Room: 224\, Bldg: C2\, AGH University\, Kraków\, Malopolskie\, Po land\, Virtual: https://events.vtools.ieee.org/m/548979 ORGANIZER:kasinski@agh.edu.pl SEQUENCE:12 SUMMARY:All-Digital Phase-Locked Loops (ADPLL): Direct Frequency Modulation [R. Bogdan Staszewski SSCS Chapter Poland] URL;VALUE=URI:https://events.vtools.ieee.org/m/548979 X-ALT-DESC:Description: <br /><p>Abstract: The past two decades has seen pr oliferation of all-digital phase-locked loops (ADPLL) for RF and high-perf ormance frequency synthesis due to their clear benefits of flexibility\, r econfigurability\, transfer function precision\, settling speed\, frequenc y modulation capability\, and amenability to integration with digital base band and application processors. When implemented in nanoscale CMOS\, the ADPLL also exhibits advantages of better performance\, lower power consump tion\, lower area and cost over the traditional analog-intensive charge-pu mp PLL. In a typical ADPLL\, a traditional VCO got directly replaced by a digitally controlled oscillator (DCO) for generating an output variable cl ock\, a traditional phase/frequency detector and a charge pump got replace d by a time-to-digital converter (TDC) for detecting phase departures of t he variable clock versus the frequency reference (FREF) clock\, and an ana log loop RC filter got replaced with a digital loop filter. The conversion gains of the DCO and TDC circuits are readily estimated and compensated u sing &ldquo\;free&rdquo\; but powerful digital logic.</p>\n<p>The first th ree talks covered the fundamentals of ADPLL\, its loop response and gear-s hifting techniques. This fourth talk will cover direct frequency modulatio n capabilities of ADPLL and DCO fundamentals.</p> END:VEVENT END:VCALENDAR