BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:Asia/Kolkata BEGIN:STANDARD DTSTART:19451014T230000 TZOFFSETFROM:+0630 TZOFFSETTO:+0530 TZNAME:IST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20260325T042247Z UID:6F0FFD24-129A-4DED-82CA-CAE1EE174D96 DTSTART;TZID=Asia/Kolkata:20260323T140000 DTEND;TZID=Asia/Kolkata:20260323T150000 DESCRIPTION:This talk presents a calibration-free recursive 1-1 MASH noise- shaping SAR\nADC implemented in 65-nm CMOS. By temporally reusing a single CDAC\, residue\namplifier (RA)\, and comparator across both stages\, the proposed architecture\ninherently eliminates inter-stage gain and offset s ensitivity without calibration or\nadditional conversion cycles. A duty cy cle correlated level-shifting (CLS) enhanced\nfloating inverter amplifier achieves 68-dB effective gain with low power overhead. A 4-\nbit MSB data- weighted averaging (DWA) scheme based on ADC/DAC dissociation\nsuppresses CDAC mismatch while remaining inactive during bit trials to minimize\nswit ching energy. The design occupies an active area of 0.081mm2\, consumes 12 .07 μW\,\nand achieves a FoMs\,DR of 172.48 dB.\n\nSpeaker(s): Shaleen\, Shaleen\n\nVirtual: https://events.vtools.ieee.org/m/549290 LOCATION:Virtual: https://events.vtools.ieee.org/m/549290 ORGANIZER:p4242prashant@gmail.com SEQUENCE:17 SUMMARY:A 1-1 MASH Noise Shaping SAR ADC with CLS Based Closed-Loop Residue Amplifier and On-Chip DWA CDAC Mismatch Correction URL;VALUE=URI:https://events.vtools.ieee.org/m/549290 X-ALT-DESC:Description: <br /><p style="text-align: justify\;">This talk pr esents a calibration-free recursive 1-1 MASH noise-shaping SAR<br>ADC impl emented in 65-nm CMOS. By temporally reusing a single CDAC\, residue<br>am plifier (RA)\, and comparator across both stages\, the proposed architectu re<br>inherently eliminates inter-stage gain and offset sensitivity withou t calibration or<br>additional conversion cycles. A duty cycle correlated level-shifting (CLS) enhanced<br>floating inverter amplifier achieves 68-d B effective gain with low power overhead. A 4-<br>bit MSB data-weighted av eraging (DWA) scheme based on ADC/DAC dissociation<br>suppresses CDAC mism atch while remaining inactive during bit trials to minimize<br>switching e nergy. The design occupies an active area of 0.081mm2\, consumes 12.07 &mu \;W\,<br>and achieves a FoMs\,DR of 172.48 dB.</p> END:VEVENT END:VCALENDAR