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DTSTART:20260308T030000
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DTSTART;TZID=America/Chicago:20260327T140000
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DESCRIPTION:Invited talk on "Static Analysis-based Security Verification on
  Modern System-on-Chips".\n\nThe session will walk through a typical verif
 ication flow: modeling assets and threats\, encoding security policies\, r
 unning static checks to detect design-level violations (e.g.\, unintended 
 data paths\, insecure register mappings\, debug backdoors)\, and interpret
 ing results to guide design fixes. Practical case studies on contemporary 
 SoC platforms will illustrate how these techniques can detect subtle vulne
 rabilities early in the design cycle\, reduce verification cost\, and comp
 lement dynamic verification and penetration testing. The talk is aimed at 
 researchers\, hardware designers\, and security engineers interested in bu
 ilding more trustworthy SoCs by integrating security verification as a fir
 st-class design step\, rather than a late add-on.\n\nSpeaker: Dr. Rasheed 
 Kibria\, University of Florida.\n\nCo-sponsored by: FLORIDA ATLANTIC UNIVE
 RSITY\n\nSpeaker(s): Rasheed \n\nVirtual: https://events.vtools.ieee.org/m
 /549383
LOCATION:Virtual: https://events.vtools.ieee.org/m/549383
ORGANIZER:sreeranjanirajendran@gmail.com
SEQUENCE:9
SUMMARY:Invited talk on "Static Analysis-based Security Verification on Mod
 ern System-on-Chips"
URL;VALUE=URI:https://events.vtools.ieee.org/m/549383
X-ALT-DESC:Description: <br /><p>Invited talk on "Static Analysis-based Sec
 urity Verification on Modern System-on-Chips".</p>\n<p>The session will wa
 lk through a typical verification flow: modeling assets and threats\, enco
 ding security policies\, running static checks to detect design-level viol
 ations (e.g.\, unintended data paths\, insecure register mappings\, debug 
 backdoors)\, and interpreting results to guide design fixes. Practical cas
 e studies on contemporary SoC platforms will illustrate how these techniqu
 es can detect subtle vulnerabilities early in the design cycle\, reduce ve
 rification cost\, and complement dynamic verification and penetration test
 ing. The talk is aimed at researchers\, hardware designers\, and security 
 engineers interested in building more trustworthy SoCs by integrating&nbsp
 \;<strong>security verification as a first-class design step</strong>\, ra
 ther than a late add-on.</p>\n<p><strong>Speaker: Dr. Rasheed Kibria\, Uni
 versity of Florida.&nbsp\;</strong></p>
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