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VERSION:2.0
PRODID:IEEE vTools.Events//EN
CALSCALE:GREGORIAN
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TZID:Asia/Kolkata
BEGIN:STANDARD
DTSTART:19451014T230000
TZOFFSETFROM:+0630
TZOFFSETTO:+0530
TZNAME:IST
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BEGIN:VEVENT
DTSTAMP:20260328T024523Z
UID:503A1B4A-E010-43A7-8B17-AC5FEA6BD4A4
DTSTART;TZID=Asia/Kolkata:20260418T100000
DTEND;TZID=Asia/Kolkata:20260418T170000
DESCRIPTION:IEEE PES University Student Branch in collaboration with IEEE C
 EDA Bangalore Chapter\, is organizing a one-day technical workshop titled 
 “Clock To Chip: Workshop on Static Timing Analysis and Place & Route (Pn
 R)”.\n\nThis workshop is designed to introduce participants to the core 
 concepts and industry practices involved in Static Timing Analysis (STA) a
 nd Physical Design (PnR)\, which are critical stages in modern VLSI chip d
 esign. Attendees will gain practical insights into timing closure\, design
  optimization\, and real-world chip implementation flows.\n\nThe session w
 ill be delivered by industry professionals\, offering participants an oppo
 rtunity to learn directly from experts and understand current trends in se
 miconductor design.\n\n[]\n\nSpeaker(s): Mayuresh Joshi\, Abhishek Kumar S
 inghania\n\nBE Block\, 6th Floor\, Seminar Hall\, PES University\, RR Camp
 us\, Bengaluru\, Karnataka\, India\, 560085
LOCATION:BE Block\, 6th Floor\, Seminar Hall\, PES University\, RR Campus\,
  Bengaluru\, Karnataka\, India\, 560085
ORGANIZER:avamsikrishna@ieee.org
SEQUENCE:8
SUMMARY:Clock To Chip: Workshop on Static Timing Analysis and PnR
URL;VALUE=URI:https://events.vtools.ieee.org/m/551251
X-ALT-DESC:Description: <br /><p data-start="397" data-end="587">IEEE PES U
 niversity Student Branch in collaboration with IEEE CEDA Bangalore Chapter
 \, is organizing a one-day technical workshop titled <strong data-start="5
 07" data-end="586">&ldquo\;Clock To Chip: Workshop on Static Timing Analys
 is and Place &amp\; Route (PnR)&rdquo\;</strong>.</p>\n<p data-start="589"
  data-end="929">This workshop is designed to introduce participants to the
  core concepts and industry practices involved in Static Timing Analysis (
 STA) and Physical Design (PnR)\, which are critical stages in modern VLSI 
 chip design. Attendees will gain practical insights into timing closure\, 
 design optimization\, and real-world chip implementation flows.</p>\n<p da
 ta-start="931" data-end="1110">The session will be delivered by industry p
 rofessionals\, offering participants an opportunity to learn directly from
  experts and understand current trends in semiconductor design.</p>\n<p st
 yle="text-align: center\;" data-start="931" data-end="1110"><img src="http
 s://events.vtools.ieee.org/vtools_ui/media/display/78096b2e-ed26-4095-aa1c
 -c0b4ad70ffdb" alt="" width="500" height="707"></p>
END:VEVENT
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