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DTSTART:20260308T030000
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DTSTART:20261101T010000
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BEGIN:VEVENT
DTSTAMP:20260408T051427Z
UID:2310B548-CEEF-44FA-BC11-88729ED7D3FF
DTSTART;TZID=America/Los_Angeles:20260403T160000
DTEND;TZID=America/Los_Angeles:20260403T170000
DESCRIPTION:Agenda: The Sacramento Valley YP Group Meeting is a coordinatio
 n and planning forum for events\n\nAgenda: \nAgenda -\n\nMeeting Agenda 
 – IEEE San Francisco Hackathon Planning\n\nDiscussion Topics\n\n1. Event
  Overview\n- Introduction to IEEE San Francisco hackathon initiative\n- Go
 als of the chip design verification event\n\n2. Date Confirmation\n- Propo
 sed date: April 29\n- Team availability and conflicts\n\n3. Event Format\n
 - Combination of Chip Making presentation + Hackathon\n- Duration and stru
 cture (half-day vs full-day)\n\n4. Hackathon Scope &amp; Ideas\n- Possible the
 mes in chip design verification\n- Problem statements (e.g.\, testbench cr
 eation\, bug detection\, coverage analysis)\n- Tools\, platforms\, and par
 ticipant level\n\n5. Roles &amp; Responsibilities\n- Judges (team members)\n- 
 Mentors/support staff\n- Event coordination roles\n\n6. Judging Criteria\n
 - Innovation\n- Technical correctness\n- Completeness and presentation\n\n
 7. Logistics &amp; Next Steps\n- Venue / virtual setup\n- Promotion and outrea
 ch\n- Timeline and action items\n\nVirtual: https://events.vtools.ieee.org
 /m/552492
LOCATION:Virtual: https://events.vtools.ieee.org/m/552492
ORGANIZER:venuskolari@gmail.com, jigarmicro@gmail.com
SEQUENCE:18
SUMMARY:The Sacramento Valley YP Group Meeting
URL;VALUE=URI:https://events.vtools.ieee.org/m/552492
X-ALT-DESC:Description: &lt;br /&gt;&lt;p&gt;Agenda: The Sacramento Valley YP Group Mee
 ting is a coordination and planning forum for events&lt;/p&gt;&lt;br /&gt;&lt;br /&gt;Agenda
 : &lt;br /&gt;&lt;p&gt;Agenda -&amp;nbsp\;&lt;/p&gt;\n&lt;p&gt;Meeting Agenda &amp;ndash\; IEEE San Franci
 sco Hackathon Planning&lt;/p&gt;\n&lt;p&gt;Discussion Topics&lt;br&gt;&lt;br&gt;1. Event Overview&lt;
 br&gt;- Introduction to IEEE San Francisco hackathon initiative&lt;br&gt;- Goals of
  the chip design verification event&lt;br&gt;&lt;br&gt;2. Date Confirmation&lt;br&gt;- Propo
 sed date: April 29&lt;br&gt;- Team availability and conflicts&lt;br&gt;&lt;br&gt;3. Event Fo
 rmat&lt;br&gt;- Combination of Chip Making presentation + Hackathon&lt;br&gt;- Duratio
 n and structure (half-day vs full-day)&lt;br&gt;&lt;br&gt;4. Hackathon Scope &amp;amp\; Id
 eas&amp;nbsp\;&lt;br&gt;- Possible themes in chip design verification&lt;br&gt;- Problem s
 tatements (e.g.\, testbench creation\, bug detection\, coverage analysis)&lt;
 br&gt;- Tools\, platforms\, and participant level&lt;br&gt;&lt;br&gt;5. Roles &amp;amp\; Resp
 onsibilities&lt;br&gt;- Judges (team members)&lt;br&gt;- Mentors/support staff&lt;br&gt;- Ev
 ent coordination roles&lt;br&gt;&lt;br&gt;6. Judging Criteria&lt;br&gt;- Innovation&lt;br&gt;- Tec
 hnical correctness&lt;br&gt;- Completeness and presentation&lt;br&gt;&lt;br&gt;7. Logistics 
 &amp;amp\; Next Steps&lt;br&gt;- Venue / virtual setup&lt;br&gt;- Promotion and outreach&lt;b
 r&gt;- Timeline and action items&lt;/p&gt;
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