BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:America/Los_Angeles BEGIN:DAYLIGHT DTSTART:20260308T030000 TZOFFSETFROM:-0800 TZOFFSETTO:-0700 RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3 TZNAME:PDT END:DAYLIGHT BEGIN:STANDARD DTSTART:20261101T010000 TZOFFSETFROM:-0700 TZOFFSETTO:-0800 RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11 TZNAME:PST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20260412T103333Z UID:9A36B2D2-4F11-49D6-A894-633D71EDBFF3 DTSTART;TZID=America/Los_Angeles:20260423T110000 DTEND;TZID=America/Los_Angeles:20260423T120000 DESCRIPTION:Title: Fractional-N Phase-Locked Loops Using Harmonic-Mixer-Bas ed Feedback and Noise Cancellation\n\nAbstract: Frequency synthesizers are an integral part of various applications\, such as wireless and wireline communication systems. The generation of frequency sources with low phase noise under limited power\, area\, and many other factors has been an ongo ing challenge over the years. Especially for the fractional-N phase-locked loops (PLLs)\, the suppression of quantization noise (Q-noise) and spurs has been one of the main challenges. Architectures based on quantization e rror cancellation\, either in the time domain using digital-to-time conver ters or in the voltage domain using digital-to-analog converters\, have be en popular in recent years. However\, the circuits used for the cancellati on are often affected by PVT-related gain errors and non-linearity\, requi ring intensive digital calibration to prevent severe performance degradati on. In this talk\, we introduce some harmonic-mixer-based fractional-N PLL architectures that avoid the amplification of the Q-noise by the loop. Wi th this concept\, we can effectively suppress the contribution of the Q-no ise at the PLL output without applying intensive calibration.\n\nTetsuya I izuka received the B.S.\, M.S.\, and Ph.D. degrees in electronic engineeri ng from the University of Tokyo\, Tokyo\, Japan\, in 2002\, 2004\, and 200 7\, respectively. From 2007 to 2009\, he was with THine Electronics Inc.\, Tokyo\, as a High-Speed Serial Interface Circuit Engineer. He joined the University of Tokyo in 2009\, where he is currently a Professor with the D epartment of Electrical Engineering and Information Systems\, School of En gineering. From 2013 to 2015\, he was a Visiting Scholar with the Universi ty of California at Los Angeles\, Los Angeles\, CA\, USA. His current rese arch interests include data conversion techniques\, high-speed analog inte grated circuits\, digitally assisted analog circuits\, and VLSI computer-a ided design.\n\nHe was a TPC member of ISSCC from 2013 to 2017 and CICC fr om 2014 to 2019. He is also serving as a member of the IEEE Asian Solid-St ate Circuits Conference (A-SSCC) and the IEEE VLSI Symposium on Circuits T echnical Program Committees. Since 2025\, he has been serving as a disting uished lecturer of the IEEE SSCS.\n\nSpeaker(s): Tetsuya\, \n\nRoom: Room ECE 269\, Bldg: Electrical and Computer Engineering Building\, 185 Stevens Way\, Seattle\, Washington\, United States\, 98195 LOCATION:Room: Room ECE 269\, Bldg: Electrical and Computer Engineering Bui lding\, 185 Stevens Way\, Seattle\, Washington\, United States\, 98195 ORGANIZER:jcrudell@uw.edu SEQUENCE:133 SUMMARY:SSCS DL Presentation - Fractional-N Phase-Locked Loops Using Harmon ic-Mixer-Based Feedback and Noise Cancellation URL;VALUE=URI:https://events.vtools.ieee.org/m/553743 X-ALT-DESC:Description: <br /><p class="MsoNormal"><strong>Title:</strong> Fractional-N Phase-Locked Loops Using Harmonic-Mixer-Based Feedback and No ise Cancellation</p>\n<p class="MsoNormal"><strong>Abstract:</strong> Freq uency synthesizers are an integral part of various applications\, such as wireless and wireline communication systems. The generation of frequency s ources with low phase noise under limited power\, area\, and many other fa ctors has been an ongoing challenge over the years. Especially for the fra ctional-N phase-locked loops (PLLs)\, the suppression of quantization nois e (Q-noise) and spurs has been one of the main challenges. Architectures b ased on quantization error cancellation\, either in the time domain using digital-to-time converters or in the voltage domain using digital-to-analo g converters\, have been popular in recent years. However\, the circuits u sed for the cancellation are often affected by PVT-related gain errors and non-linearity\, requiring intensive digital calibration to prevent severe performance degradation. In this talk\, we introduce some harmonic-mixer- based fractional-N PLL architectures that avoid the amplification of the Q -noise by the loop. With this concept\, we can effectively suppress the co ntribution of the Q-noise at the PLL output without applying intensive cal ibration.</p>\n<p class="MsoNormal" style="text-align: justify\;">Tetsuya Iizuka received the B.S.\, M.S.\, and Ph.D. degrees in electronic engineer ing from the University of Tokyo\, Tokyo\, Japan\, in 2002\, 2004\, and 20 07\, respectively. From 2007 to 2009\, he was with THine Electronics Inc.\ , Tokyo\, as a High-Speed Serial Interface Circuit Engineer. He joined the University of Tokyo in 2009\, where he is currently a Professor with the Department of Electrical Engineering and Information Systems\, School of E ngineering. From 2013 to 2015\, he was a Visiting Scholar with the Univers ity of California at Los Angeles\, Los Angeles\, CA\, USA. His current res earch interests include data conversion techniques\, high-speed analog int egrated circuits\, digitally assisted analog circuits\, and VLSI computer- aided design.</p>\n<p class="MsoNormal" style="text-align: justify\;">He w as a TPC member of ISSCC from 2013 to 2017 and CICC from 2014 to 2019. He is also serving as a member of the IEEE Asian Solid-State Circuits Confere nce (A-SSCC) and the IEEE VLSI Symposium on Circuits Technical Program Com mittees. Since 2025\, he has been serving as a distinguished lecturer of t he IEEE SSCS.</p> END:VEVENT END:VCALENDAR