BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:America/Los_Angeles BEGIN:DAYLIGHT DTSTART:20260308T030000 TZOFFSETFROM:-0800 TZOFFSETTO:-0700 RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3 TZNAME:PDT END:DAYLIGHT BEGIN:STANDARD DTSTART:20261101T010000 TZOFFSETFROM:-0700 TZOFFSETTO:-0800 RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11 TZNAME:PST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20260412T102009Z UID:1DA7A3C6-79A7-49A9-8A97-2C65D5CB1802 DTSTART;TZID=America/Los_Angeles:20260421T103000 DTEND;TZID=America/Los_Angeles:20260421T113000 DESCRIPTION:Abstract: Nowadays\, both digital and analog electronics are re aching fundamental limits that will require revolutionary approaches to sa tisfy the power/bandwidth requirements of the next generation of data-driv en applications.\n\nIn the first part of the talk\, analog and digital sig nal processing will be compared in terms of power efficiency by highlighti ng the presence of a thermodynamic upper-bound which relates dynamic range \, bandwidth and power dissipation. To circumvent this limit\, in the seco nd part of the talk\, the quantized-analog signal processing will be intro duced. In such approach\, analog and digital domains are merged together i n a more fluid scenario compared to traditional mixed-signal circuits avoi ding the needs of rigid interfaces such as analog-to-digital and digital-t o-analog converters.\n\nIt will be shown that the quantized-analog signal processing leads to superior power efficiency and flexibility compared to its analog counterpart and it represents a good candidate for the developm ent of a new generation of mixed signal integrated circuits. The effectiv eness of the proposed solutions will be demonstrated through simulations a nd measurement results.\n\nAntonio Liscidini received the Laurea (summa cu m laude) and Ph.D. degrees in electrical engineering from the University o f Pavia\, Pavia\, Italy\, in 2002 and 2006\, respectively.\n\nHe was a sum mer Intern with National Semiconductors\, Santa Clara\, CA\, USA\, in 2003 \, studying poly phase filters and CMOS low-noise amplifiers. From 2008 to 2012\, he was an Assistant Professor with the University of Pavia and a c onsultant with Marvell Semiconductors\, Pavia\, in the area of integrated circuit design. In 2012\, he moved to the Edward S. Rogers Sr. Department of Electrical and Computer Engineering\, University of Toronto\, Toronto\, ON\, Canada\, where he is currently Full Professor and Associate Chair Gr aduate. From 2019 to 2022 he was consultant for Huawei Technology Group in the area of RFIC for optical communication and SerDes. Since 2022 has bee n consultant for Marvell Technology group. His research interests are focu sed on analog mixed signal interfaces with particular emphasis on the impl ementations of transceivers and frequency synthesizers for wireless-wireli ne communication and ultra-low power applications.\n\nDr. Liscidini was a recipient of the Best Student Paper Award at the IEEE 2005 Symposium on VL SI Circuits\, co-recipient of the Best Invited Paper Award at the 2011 IEE E CICC and Best Student Paper Award at the 2018 IEEE ESSCIRC.\n\nHe is cur rently Associate Editor in Chief for IEEE Transactions on Circuits and Sys tems II: Express Briefs. He has served as an Associate/Guest Editor for se veral IEEE Journal including: Open Journal of Solid-State Circuit Society\ , Transactions on Circuits and Systems II: Express Briefs and\, Journal of Solid-State Circuits\, RFIC Virtual Journal and Solid State Circuit Lette rs. He has been member for many TPC conferences including ISSCC\, ESSCIRC\ , and CICC. Between 2016 and 2018\, he has been a Distinguished Lecturer o f the IEEE Solid-State Circuits Society. Since 2026\, he is a IEEE Fellow. \n\nSpeaker(s): Professor Antonio Liscidini\, \n\nRoom: Room 037\, Bldg: E lectrical and Computer Engineering Building\, 185 W Stevens Wy NE \, Seat tle\, Washington\, United States\, 98195 LOCATION:Room: Room 037\, Bldg: Electrical and Computer Engineering Buildin g\, 185 W Stevens Wy NE \, Seattle\, Washington\, United States\, 98195 ORGANIZER:jcrudell@uw.edu SEQUENCE:23 SUMMARY:SSCS DL Presentation : Quantized-Analog Signal Processing URL;VALUE=URI:https://events.vtools.ieee.org/m/553782 X-ALT-DESC:Description: <br /><p class="MsoNormal" style="text-align: justi fy\;"><span lang="EN-CA" style="font-size: 11.0pt\; mso-bidi-font-weight: bold\;"><strong>Abstract:</strong> Nowadays\, both digital and analog elec tronics are reaching fundamental limits that will require revolutionary ap proaches to satisfy the power/bandwidth requirements of the next generatio n of data-driven applications.</span></p>\n<p class="MsoNormal" style="tex t-align: justify\;"><span lang="EN-CA" style="font-size: 11.0pt\; mso-bidi -font-weight: bold\;">In the first part of the talk\, </span><span lang="E N-CA" style="font-size: 11.0pt\;">analog and digital signal processing wil l be compared in terms of power efficiency by highlighting the presence of a thermodynamic upper-bound which relates dynamic range\, bandwidth and p ower dissipation. To circumvent this limit\, in the second part of the tal k\, the quantized-analog signal processing will be introduced. In such app roach\, analog and digital domains are merged together in a more fluid sce nario compared to traditional mixed-signal circuits avoiding the needs of rigid interfaces such as analog-to-digital and digital-to-analog converter s. </span></p>\n<p class="MsoNormal" style="text-align: justify\;"><span l ang="EN-CA" style="font-size: 11.0pt\;">It will be shown that the quantize d-analog signal processing leads to superior power efficiency and flexibil ity compared to its analog counterpart and it represents a good candidate for the development of a new generation of mixed signal integrated circuit s. <span style="mso-spacerun: yes\;">&nbsp\;</span>The effectiveness of th e proposed solutions will be demonstrated through simulations and measurem ent results.</span></p>\n<p class="MsoNormal" style="text-align: justify\; "><strong style="mso-bidi-font-weight: normal\;"><span lang="EN-CA" style= "font-size: 11.0pt\; mso-ascii-font-family: Calibri\; mso-hansi-font-famil y: Calibri\; mso-bidi-font-family: Calibri\;">Antonio Liscidini</span></st rong><span lang="EN-CA" style="font-size: 11.0pt\; mso-ascii-font-family: Calibri\; mso-hansi-font-family: Calibri\; mso-bidi-font-family: Calibri\; "> received the Laurea (summa cum laude) and Ph.D. degrees in electrical e ngineering from the University of Pavia\, Pavia\, Italy\, in 2002 and 2006 \, respectively.</span></p>\n<p class="MsoNormal" style="text-align: justi fy\;"><span lang="EN-CA" style="font-size: 11.0pt\; mso-ascii-font-family: Calibri\; mso-hansi-font-family: Calibri\; mso-bidi-font-family: Calibri\ ;">He was a summer Intern with National Semiconductors\, Santa Clara\, CA\ , USA\, in 2003\, studying poly phase filters and CMOS low-noise amplifier s. From 2008 to 2012\, he was an Assistant Professor with the University o f Pavia and a consultant with Marvell Semiconductors\, Pavia\, in the area of integrated circuit design. In 2012\, he moved to the Edward S. Rogers Sr. Department of Electrical and Computer Engineering\, University of Toro nto\, Toronto\, ON\, Canada\, where he is currently Full<span style="mso-s pacerun: yes\;">&nbsp\; </span>Professor and Associate Chair Graduate. Fro m 2019 to 2022 he was consultant for Huawei Technology Group in the area o f RFIC for optical communication and SerDes. Since 2022 has been consultan t for Marvell Technology group. His research interests are focused on anal og mixed signal interfaces with particular emphasis on the implementations of transceivers and frequency synthesizers for wireless-wireline communic ation and ultra-low power applications.</span></p>\n<p class="MsoNormal" s tyle="text-align: justify\;"><span lang="EN-CA" style="font-size: 11.0pt\; mso-ascii-font-family: Calibri\; mso-hansi-font-family: Calibri\; mso-bid i-font-family: Calibri\;">Dr. Liscidini was a recipient of the Best Studen t Paper Award at the IEEE 2005 Symposium on VLSI Circuits\, co-recipient o f the Best Invited Paper Award at the 2011 IEEE CICC and Best Student Pape r Award at the 2018 IEEE ESSCIRC. </span></p>\n<p class="MsoNormal" style= "text-align: justify\;"><span lang="EN-CA" style="font-size: 11.0pt\; mso- ascii-font-family: Calibri\; mso-hansi-font-family: Calibri\; mso-bidi-fon t-family: Calibri\;">He is currently Associate Editor in Chief for IEEE Tr ansactions on Circuits and Systems II: Express Briefs.<span style="mso-spa cerun: yes\;">&nbsp\; </span>He has served as an Associate/Guest Editor fo r several IEEE Journal including: Open Journal of Solid-State Circuit Soci ety\, Transactions on Circuits and Systems II: Express Briefs and\, Journa l of Solid-State Circuits\, RFIC Virtual Journal and Solid State Circuit L etters. He has been member for many TPC conferences including ISSCC\, ESSC IRC\, and CICC. Between 2016 and 2018\, he has been a Distinguished Lectur er of the IEEE Solid-State Circuits Society. Since 2026\, he is a IEEE Fel low.</span></p>\n<p class="MsoNormal" style="text-align: justify\;"><span lang="EN-CA" style="font-size: 11.0pt\; mso-ascii-font-family: Calibri\; m so-hansi-font-family: Calibri\; mso-bidi-font-family: Calibri\;"><img src= "https://events.vtools.ieee.org/vtools_ui/media/display/d83311a8-a688-4ec3 -8159-4a29ea999093"></span></p> END:VEVENT END:VCALENDAR