BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:America/New_York BEGIN:DAYLIGHT DTSTART:20260308T030000 TZOFFSETFROM:-0500 TZOFFSETTO:-0400 RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3 TZNAME:EDT END:DAYLIGHT BEGIN:STANDARD DTSTART:20261101T010000 TZOFFSETFROM:-0400 TZOFFSETTO:-0500 RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11 TZNAME:EST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20260428T024644Z UID:267B6BEB-BAC8-4006-9B4B-019DDD9DC67B DTSTART;TZID=America/New_York:20260518T100000 DTEND;TZID=America/New_York:20260518T113000 DESCRIPTION:IEEE Electronic Packaging Society Toronto is proud to invite yo u to a virtual distinguished lecture by Dr. Mukta Farooq of IBM research.\ n\nJoin us Monday\, 11 May 2026 at 10AM (ET)\n\nUpdate: Join us Monday\, 1 8 May 2026 at 10AM (ET)\n\nAbstract\n------------------------------------- --------------------------\n\nWhile silicon scaling has reached astonishin g levels over the last half century\, there has not been a corresponding l evel of scaling in electronic packaging technology. However\, Artificial I ntelligence (AI) architectures are now changing the landscape\, increasing ly moving us towards chiplets and advanced packaging technology\, especial ly Heterogeneous Integration (HI). What are these unique requirements of A I which are driving the need for HI? What are some of the unique challenge s in semiconductor and packaging technologies that must be overcome to mak e this successful? This seminar will discuss key HI methods including inte rposers\, fan out wafer level processing\, silicon bridges\, and 3D integr ation. We will look at their attributes as well as their challenges\, to d etermine how they can be leveraged to achieve AI architectures.\n\n------- --------------------------------------------------------\n\n-------------- -------------------------------------------------\n\nSpeaker(s): Dr. Mukta Farooq\, \n\nVirtual: https://events.vtools.ieee.org/m/554791 LOCATION:Virtual: https://events.vtools.ieee.org/m/554791 ORGANIZER:jiupeng.zhang@mail.utoronto.ca SEQUENCE:31 SUMMARY:[IEEE CAS04/ED15/EP21/PHO36 EPS Distinguished Lecture] Heterogeneou s Integration and Advanced Packaging for AI and the Chiplet ERA URL;VALUE=URI:https://events.vtools.ieee.org/m/554791 X-ALT-DESC:Description: <br /><p style="language: en-CA\; margin-top: 0pt\; margin-bottom: 0pt\; margin-left: 0in\; text-align: left\; direction: ltr \; unicode-bidi: embed\; mso-line-break-override: none\; word-break: norma l\; punctuation-wrap: hanging\;"><span style="font-size: 14pt\; font-famil y: 'times new roman'\, times\, serif\; color: black\;">IEEE Electronic Pac kaging Society Toronto is proud to invite you to a virtual distinguished l ecture by Dr. Mukta Farooq of IBM research.</span></p>\n<p style="language : en-CA\; margin-top: 0pt\; margin-bottom: 0pt\; margin-left: 0in\; text-a lign: left\; direction: ltr\; unicode-bidi: embed\; mso-line-break-overrid e: none\; word-break: normal\; punctuation-wrap: hanging\;"><s><span style ="font-size: 14pt\; font-family: 'times new roman'\, times\, serif\; color : black\;">Join us Monday\, 11 May 2026 at 10AM (ET)&nbsp\;</span></s></p> \n<p style="language: en-CA\; margin-top: 0pt\; margin-bottom: 0pt\; margi n-left: 0in\; text-align: left\; direction: ltr\; unicode-bidi: embed\; ms o-line-break-override: none\; word-break: normal\; punctuation-wrap: hangi ng\;"><span style="font-size: 14pt\; font-family: 'times new roman'\, time s\, serif\; color: black\;">Update: Join us Monday\, 18 May 2026 at 10AM ( ET)&nbsp\;</span></p>\n<p style="language: en-CA\; margin-top: 0pt\; margi n-bottom: 0pt\; margin-left: 0in\; text-align: left\; direction: ltr\; uni code-bidi: embed\; mso-line-break-override: none\; word-break: normal\; pu nctuation-wrap: hanging\;">&nbsp\;</p>\n<p style="language: en-CA\; margin -top: 0pt\; margin-bottom: 0pt\; margin-left: 0in\; text-align: left\; dir ection: ltr\; unicode-bidi: embed\; mso-line-break-override: none\; word-b reak: normal\; punctuation-wrap: hanging\;"><strong><span style="font-size : 18pt\; font-family: 'times new roman'\, times\, serif\; color: black\;"> Abstract</span></strong></p>\n<hr>\n<p class="MsoNormal" style="text-align : justify\; text-indent: 36.0pt\;"><span lang="EN-US" style="font-size: 14 pt\; font-family: 'times new roman'\, times\, serif\;">While silicon scali ng has reached astonishing levels over the last half century\, there has n ot been a corresponding level of scaling in electronic packaging technolog y. However\, Artificial Intelligence (AI) architectures are now changing t he landscape\, increasingly moving us towards chiplets and advanced packag ing technology\, especially Heterogeneous Integration (HI). What are these unique requirements of AI which are driving the need for HI? What are som e of the unique challenges in semiconductor and packaging technologies tha t must be overcome to make this successful? This seminar will discuss key HI methods including interposers\, fan out wafer level processing\, silico n bridges\, and 3D integration. We will look at their attributes as well a s their challenges\, to determine how they can be leveraged to achieve AI architectures. </span></p>\n<p style="margin-top: 0pt\; margin-bottom: 0pt \; margin-left: 0in\; direction: ltr\; unicode-bidi: embed\; word-break: n ormal\; text-align: justify\;">&nbsp\;</p>\n<hr>\n<p style="margin-top: 0p t\; margin-bottom: 0pt\; margin-left: 0in\; direction: ltr\; unicode-bidi: embed\; word-break: normal\;"><img style="display: block\; margin-left: a uto\; margin-right: auto\;" src="https://events.vtools.ieee.org/vtools_ui/ media/display/793ee5de-d090-45c9-949a-542b95d18423" width="758" height="42 5"></p>\n<hr>\n<p style="language: en-CA\; margin-top: 0pt\; margin-bottom : 0pt\; margin-left: 0in\; text-align: left\; direction: ltr\; unicode-bid i: embed\; mso-line-break-override: none\; word-break: normal\; punctuatio n-wrap: hanging\;">&nbsp\;</p> END:VEVENT END:VCALENDAR