BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:America/New_York BEGIN:DAYLIGHT DTSTART:20260308T030000 TZOFFSETFROM:-0500 TZOFFSETTO:-0400 RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3 TZNAME:EDT END:DAYLIGHT BEGIN:STANDARD DTSTART:20261101T010000 TZOFFSETFROM:-0400 TZOFFSETTO:-0500 RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11 TZNAME:EST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20260414T023958Z UID:267B6BEB-BAC8-4006-9B4B-019DDD9DC67B DTSTART;TZID=America/New_York:20260511T100000 DTEND;TZID=America/New_York:20260511T233000 DESCRIPTION:IEEE Electronic Packaging Society Toronto is proud to invite yo u to a virtual distinguished lecture by Dr. Mukta Farooq of IBM research.\ n\nJoin us Monday\, 11 May 2026 at 10AM (ET)\n\nAbstract\n---------------- -----------------------------------------------\n\nWhile silicon scaling h as reached astonishing levels over the last half century\, there has not b een a corresponding level of scaling in electronic packaging technology. H owever\, Artificial Intelligence (AI) architectures are now changing the l andscape\, increasingly moving us towards chiplets and advanced packaging technology\, especially Heterogeneous Integration (HI). What are these uni que requirements of AI which are driving the need for HI? What are some of the unique challenges in semiconductor and packaging technologies that mu st be overcome to make this successful? This seminar will discuss key HI m ethods including interposers\, fan out wafer level processing\, silicon br idges\, and 3D integration. We will look at their attributes as well as th eir challenges\, to determine how they can be leveraged to achieve AI arch itectures.\n\n------------------------------------------------------------ ---\n\n---------------------------------------------------------------\n\n Speaker(s): Dr. Mukta Farooq\, \n\nVirtual: https://events.vtools.ieee.org /m/554791 LOCATION:Virtual: https://events.vtools.ieee.org/m/554791 ORGANIZER:jiupeng.zhang@mail.utoronto.ca SEQUENCE:29 SUMMARY:[IEEE CAS04/ED15/EP21/PHO36 EPS Distinguished Lecture] Heterogeneou s Integration and Advanced Packaging for AI and the Chiplet ERA URL;VALUE=URI:https://events.vtools.ieee.org/m/554791 X-ALT-DESC:Description: <br /><p style="language: en-CA\; margin-top: 0pt\; margin-bottom: 0pt\; margin-left: 0in\; text-align: left\; direction: ltr \; unicode-bidi: embed\; mso-line-break-override: none\; word-break: norma l\; punctuation-wrap: hanging\;"><span style="font-size: 14pt\; font-famil y: 'times new roman'\, times\, serif\; color: black\;">IEEE Electronic Pac kaging Society Toronto is proud to invite you to a virtual distinguished l ecture by Dr. Mukta Farooq of IBM research.</span></p>\n<p style="language : en-CA\; margin-top: 0pt\; margin-bottom: 0pt\; margin-left: 0in\; text-a lign: left\; direction: ltr\; unicode-bidi: embed\; mso-line-break-overrid e: none\; word-break: normal\; punctuation-wrap: hanging\;"><span style="f ont-size: 14pt\; font-family: 'times new roman'\, times\, serif\; color: b lack\;">Join us Monday\, 11 May 2026 at 10AM (ET)</span></p>\n<p style="la nguage: en-CA\; margin-top: 0pt\; margin-bottom: 0pt\; margin-left: 0in\; text-align: left\; direction: ltr\; unicode-bidi: embed\; mso-line-break-o verride: none\; word-break: normal\; punctuation-wrap: hanging\;">&nbsp\;< /p>\n<p style="language: en-CA\; margin-top: 0pt\; margin-bottom: 0pt\; ma rgin-left: 0in\; text-align: left\; direction: ltr\; unicode-bidi: embed\; mso-line-break-override: none\; word-break: normal\; punctuation-wrap: ha nging\;">&nbsp\;</p>\n<p style="language: en-CA\; margin-top: 0pt\; margin -bottom: 0pt\; margin-left: 0in\; text-align: left\; direction: ltr\; unic ode-bidi: embed\; mso-line-break-override: none\; word-break: normal\; pun ctuation-wrap: hanging\;"><strong><span style="font-size: 18pt\; font-fami ly: 'times new roman'\, times\, serif\; color: black\;">Abstract</span></s trong></p>\n<hr>\n<p class="MsoNormal" style="text-align: justify\; text-i ndent: 36.0pt\;"><span lang="EN-US" style="font-size: 14pt\; font-family: 'times new roman'\, times\, serif\;">While silicon scaling has reached ast onishing levels over the last half century\, there has not been a correspo nding level of scaling in electronic packaging technology. However\, Artif icial Intelligence (AI) architectures are now changing the landscape\, inc reasingly moving us towards chiplets and advanced packaging technology\, e specially Heterogeneous Integration (HI). What are these unique requiremen ts of AI which are driving the need for HI? What are some of the unique ch allenges in semiconductor and packaging technologies that must be overcome to make this successful? This seminar will discuss key HI methods includi ng interposers\, fan out wafer level processing\, silicon bridges\, and 3D integration. We will look at their attributes as well as their challenges \, to determine how they can be leveraged to achieve AI architectures. </s pan></p>\n<p style="margin-top: 0pt\; margin-bottom: 0pt\; margin-left: 0i n\; direction: ltr\; unicode-bidi: embed\; word-break: normal\; text-align : justify\;">&nbsp\;</p>\n<hr>\n<p style="margin-top: 0pt\; margin-bottom: 0pt\; margin-left: 0in\; direction: ltr\; unicode-bidi: embed\; word-brea k: normal\;"><img style="display: block\; margin-left: auto\; margin-right : auto\;" src="https://events.vtools.ieee.org/vtools_ui/media/display/98fe ab64-d7c1-4a88-ae7b-1c308a21c3e0" width="743" height="418"></p>\n<hr>\n<p style="language: en-CA\; margin-top: 0pt\; margin-bottom: 0pt\; margin-lef t: 0in\; text-align: left\; direction: ltr\; unicode-bidi: embed\; mso-lin e-break-override: none\; word-break: normal\; punctuation-wrap: hanging\;" >&nbsp\;</p> END:VEVENT END:VCALENDAR