BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:America/Los_Angeles BEGIN:DAYLIGHT DTSTART:20260308T030000 TZOFFSETFROM:-0800 TZOFFSETTO:-0700 RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3 TZNAME:PDT END:DAYLIGHT BEGIN:STANDARD DTSTART:20261101T010000 TZOFFSETFROM:-0700 TZOFFSETTO:-0800 RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11 TZNAME:PST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20260415T003001Z UID:9CD652F9-BEB4-464B-A58E-92A69F2CFA39 DTSTART;TZID=America/Los_Angeles:20260319T163000 DTEND;TZID=America/Los_Angeles:20260319T173000 DESCRIPTION:The continued demand for higher data rates in modern electronic s has driven the evolution of high-speed transceivers\, particularly withi n complex multi-die and chiplet architectures. These advanced packaging sc hemes\, including 3D IC integration and chip-to-chip/chip-to-interposer co nfigurations\, introduce unprecedented signal integrity challenges due to inter-symbol interference\, channel loss\, dispersion and parasitic coupli ng effects. Accurate verification of these intricate high-speed links nece ssitates a sophisticated approach that can account for both the non-linear behavior of custom-designed transceivers including channel paths (requiri ng SPICE-level analysis) and the algorithmic equalization schemes (like CT LE and DFE) typically described by IBIS-AMI models. Traditional verificati on flows often struggle to seamlessly integrate these diverse modeling par adigms\, leading to fragmented analysis and increased design iterations. T his presentation highlights a unified simulation methodology that combines SPICE-level circuit simulation with IBIS-AMI modeling for comprehensive t ransceiver verification in multi-die and chiplet applications. The approac h enables designers to precisely analyze custom transceiver IP while simul taneously integrating vendor-provided IBIS-AMI models for external chiplet s\, ensuring accurate representation of the entire high-speed link. The me thodology supports essential elements such as S-parameter models\, lossy c oupled transmission lines\, and DSPF from parasitic extractions\, all crit ical for modeling the physical realities of multi-die environments. The in tegrated approach\, demonstrated with examples using Siemens EDA's Solido Simulation Suite and HyperLynx tools\, provides consistent\, accurate anal ysis from circuit-level transceivers up to system-level interconnects\, si gnificantly streamlining verification and accelerating time-to-market for next-generation chiplet-based designs.\n\nCo-sponsored by: Siemens EDA\n\n Speaker(s): Dr. Scott Wedge\, \n\n5001 Great America Parkway\, Santa Clara \, California\, United States\, 95054 LOCATION:5001 Great America Parkway\, Santa Clara\, California\, United Sta tes\, 95054 ORGANIZER:wedge@ieee.org SEQUENCE:22 SUMMARY:Enabling Advanced Transceiver Verification for Chiplet Architecture s URL;VALUE=URI:https://events.vtools.ieee.org/m/555028 X-ALT-DESC:Description: <br /><p>The continued demand for higher data rates in modern electronics has driven the evolution of high-speed transceivers \, particularly within complex multi-die and chiplet architectures. These advanced packaging schemes\, including 3D IC integration and chip-to-chip/ chip-to-interposer configurations\, introduce unprecedented signal integri ty challenges due to inter-symbol interference\, channel loss\, dispersion and parasitic coupling effects. Accurate verification of these intricate high-speed links necessitates a sophisticated approach that can account fo r both the non-linear behavior of custom-designed transceivers including c hannel paths (requiring SPICE-level analysis) and the algorithmic equaliza tion schemes (like CTLE and DFE) typically described by IBIS-AMI models. T raditional verification flows often struggle to seamlessly integrate these diverse modeling paradigms\, leading to fragmented analysis and increased design iterations. This presentation highlights a unified simulation meth odology that combines SPICE-level circuit simulation with IBIS-AMI modelin g for comprehensive transceiver verification in multi-die and chiplet appl ications. The approach enables designers to precisely analyze custom trans ceiver IP while simultaneously integrating vendor-provided IBIS-AMI models for external chiplets\, ensuring accurate representation of the entire hi gh-speed link. The methodology supports essential elements such as S-param eter models\, lossy coupled transmission lines\, and DSPF from parasitic e xtractions\, all critical for modeling the physical realities of multi-die environments. The integrated approach\, demonstrated with examples using Siemens EDA's Solido Simulation Suite and HyperLynx tools\, provides consi stent\, accurate analysis from circuit-level transceivers up to system-lev el interconnects\, significantly streamlining verification and acceleratin g time-to-market for next-generation chiplet-based designs.</p> END:VEVENT END:VCALENDAR