BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:Africa/Nairobi BEGIN:STANDARD DTSTART:19420801T001500 TZOFFSETFROM:+0245 TZOFFSETTO:+0300 TZNAME:EAT END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20260423T113327Z UID:8E0A21D5-2506-4BCC-AAA8-B4A9D5C448E5 DTSTART;TZID=Africa/Nairobi:20260424T150000 DTEND;TZID=Africa/Nairobi:20260424T170000 DESCRIPTION:This session covers the design of multi-cycle and pipelined arc hitectures in RISC-V systems. It introduces the key registers used in a mu lti-cycle core\, explains how instructions are executed across stages. The session also examines pipeline hazards\, their impact on performance and techniques for improving overall processor efficiency.\n\nSpeaker(s): Jaco b Kirera\, Cynthia Maina\, Felix Onsongo\n\nRoom: MSB 5\, Bldg: Strathmore University\, Nairobi\, Nairobi\, Kenya LOCATION:Room: MSB 5\, Bldg: Strathmore University\, Nairobi\, Nairobi\, Ke nya ORGANIZER:azharahmedtakoy4444@gmail.com SEQUENCE:20 SUMMARY:RISC-V Workshop Session 3: Multi-cycle Core URL;VALUE=URI:https://events.vtools.ieee.org/m/556693 X-ALT-DESC:Description: <br /><p>This session covers the design of multi-cy cle and pipelined architectures in RISC-V systems. It introduces the key r egisters used in a multi-cycle core\, explains how instructions are execut ed across stages. The session also examines pipeline hazards\, their impac t on performance and techniques for improving overall processor efficiency .</p> END:VEVENT END:VCALENDAR