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DESCRIPTION:Abstract: AI is changing not only the applications we build\, b
 ut also the way we design the chips that power them. This talk explores ho
 w we can rethink chip design in the age of AI from two complementary direc
 tions: using AI to automate and improve chip design\, and building special
 ized chips that make AI dramatically more efficient.\n\nOn the design side
 \, we present Agentic-RL gLayout\, a reinforcement-learning framework for 
 analog layout generation that replaces manual heuristics with goal-driven 
 planning and self-correction. Built on open-source tools such as OpenROAD\
 , gLayout\, and OpenFASOC\, it enables cleaner\, more compact\, and rule-c
 ompliant layouts with far less manual effort. On the architecture side\, w
 e present a hardware-software co-design stack for efficient edge AI\, redu
 cing latency and energy in LLM inference. By co-optimizing models\, precis
 ion\, and accelerator design\, this approach supports fast\, privacy-prese
 rving inference under tight power constraints.\nTaken together\, these eff
 orts illustrate a broader shift toward open\, AI-enabled chip design flows
  and domain-specific AI hardware. The result is a faster\, more automated\
 , and more accessible path to silicon in the age of AI.\n\nSpeaker(s): Meh
 di\, \n\nRoom: 3142\, Bldg: EIT\, ECE Department\, 200 University Ave. W.\
 , Waterloo\, Ontario\, Canada\, N2L 3G4
LOCATION:Room: 3142\, Bldg: EIT\, ECE Department\, 200 University Ave. W.\,
  Waterloo\, Ontario\, Canada\, N2L 3G4
ORGANIZER:leo.qi@uwaterloo.ca
SEQUENCE:18
SUMMARY:SSCS Distinguished Lecture: &quot;Rethinking Chip Design in the Age of A
 I&quot;
URL;VALUE=URI:https://events.vtools.ieee.org/m/556807
X-ALT-DESC:Description: &lt;br /&gt;&lt;p class=&quot;western&quot; style=&quot;line-height: 100%\;
  orphans: 2\; widows: 2\; margin-bottom: 0cm\;&quot;&gt;&lt;span style=&quot;font-variant:
  normal\;&quot;&gt;&lt;span style=&quot;color: #242424\;&quot;&gt;&lt;span style=&quot;font-family: Segoe 
 UI\, Segoe UI Web (West European)\;&quot;&gt;&lt;span style=&quot;font-size: xx-small\;&quot;&gt;&lt;
 span style=&quot;letter-spacing: normal\;&quot;&gt;&lt;span style=&quot;font-style: normal\;&quot;&gt;&lt;
 strong&gt;Abstract: &lt;/strong&gt;&lt;/span&gt;&lt;/span&gt;&lt;/span&gt;&lt;/span&gt;&lt;/span&gt;&lt;/span&gt;&lt;span 
 style=&quot;font-variant: normal\;&quot;&gt;&lt;span style=&quot;color: #242424\;&quot;&gt;&lt;span style=
 &quot;font-family: Segoe UI\, Segoe UI Web (West European)\;&quot;&gt;&lt;span style=&quot;font
 -size: xx-small\;&quot;&gt;&lt;span style=&quot;letter-spacing: normal\;&quot;&gt;&lt;span style=&quot;fon
 t-style: normal\;&quot;&gt;&lt;span style=&quot;font-weight: normal\;&quot;&gt;AI is changing not 
 only the applications we build\, but also the way we design the chips that
  power them. This talk explores how we can rethink chip design in the age 
 of AI from two complementary directions: using AI to automate and improve 
 chip design\, and building specialized chips that make AI dramatically mor
 e efficient.&lt;/span&gt;&lt;/span&gt;&lt;/span&gt;&lt;/span&gt;&lt;/span&gt;&lt;/span&gt;&lt;/span&gt;&lt;/p&gt;\n&lt;p clas
 s=&quot;western&quot; style=&quot;line-height: 100%\; orphans: 2\; widows: 2\; margin-bot
 tom: 0cm\;&quot;&gt;&lt;br&gt;&lt;span style=&quot;font-variant: normal\;&quot;&gt;&lt;span style=&quot;color: #
 242424\;&quot;&gt;&lt;span style=&quot;font-family: Segoe UI\, Segoe UI Web (West European
 )\;&quot;&gt;&lt;span style=&quot;font-size: xx-small\;&quot;&gt;&lt;span style=&quot;letter-spacing: norm
 al\;&quot;&gt;&lt;span style=&quot;font-style: normal\;&quot;&gt;&lt;span style=&quot;font-weight: normal\
 ;&quot;&gt;On the design side\, we present Agentic-RL gLayout\, a reinforcement-le
 arning framework for analog layout generation that replaces manual heurist
 ics with goal-driven planning and self-correction. Built on open-source to
 ols such as OpenROAD\, gLayout\, and OpenFASOC\, it enables cleaner\, more
  compact\, and rule-compliant layouts with far less manual effort. On the 
 architecture side\, we present a hardware-software co-design stack for eff
 icient edge AI\, reducing latency and energy in LLM inference. By co-optim
 izing models\, precision\, and accelerator design\, this approach supports
  fast\, privacy-preserving inference under tight power constraints.&lt;/span&gt;
 &lt;/span&gt;&lt;/span&gt;&lt;/span&gt;&lt;/span&gt;&lt;/span&gt;&lt;/span&gt;&lt;br&gt;&lt;span style=&quot;font-variant: n
 ormal\;&quot;&gt;&lt;span style=&quot;color: #242424\;&quot;&gt;&lt;span style=&quot;font-family: Segoe UI
 \, Segoe UI Web (West European)\;&quot;&gt;&lt;span style=&quot;font-size: xx-small\;&quot;&gt;&lt;sp
 an style=&quot;letter-spacing: normal\;&quot;&gt;&lt;span style=&quot;font-style: normal\;&quot;&gt;&lt;sp
 an style=&quot;font-weight: normal\;&quot;&gt;Taken together\, these efforts illustrate
  a broader shift toward open\, AI-enabled chip design flows and domain-spe
 cific AI hardware. The result is a faster\, more automated\, and more acce
 ssible path to silicon in the age of AI.&lt;/span&gt;&lt;/span&gt;&lt;/span&gt;&lt;/span&gt;&lt;/span
 &gt;&lt;/span&gt;&lt;/span&gt;&lt;/p&gt;
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