BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:America/Los_Angeles BEGIN:DAYLIGHT DTSTART:20260308T030000 TZOFFSETFROM:-0800 TZOFFSETTO:-0700 RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3 TZNAME:PDT END:DAYLIGHT BEGIN:STANDARD DTSTART:20261101T010000 TZOFFSETFROM:-0700 TZOFFSETTO:-0800 RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11 TZNAME:PST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20260428T092248Z UID:5D168CF0-648B-4219-A55E-CBCCA7DE1157 DTSTART;TZID=America/Los_Angeles:20260507T100000 DTEND;TZID=America/Los_Angeles:20260507T110000 DESCRIPTION:Technical seminar by Professor David Keezer\, IEEE Life Fellow\ , Chair Professor at EIT\, Ningbo\n\nToday’s integrated circuits may con tain billions of transistors and operate at multiple gigahertz clock rates . The communication port input and output aggregate bandwidths can easily exceed a terahertz (e.g. 800G and 1.6T PCIe and fiber-optic ports). Furthe rmore\, some ICs support multiple high-speed communication ports as well a s high-performance analog/RF signals. All these critical features need pre cise testing to ensure product quality. While existing automated test equi pment (ATE) can handle the bulk of “mainstream” IC test requirements\, they are not well-suited for these most advanced applications and are not easily adapted to new test challenges of future devices that may use enti rely new signaling protocols. There is therefore a “gap” between the a bility of ATE and the test needs of the most advanced devices. To address this problem\, we are assembling an FPGA-based test-development platform t hat can quickly adapt to future test requirements. This presentation will describe the strategy and system architecture and show some early demonstr ations for testing mixed analog/digital ICs as well as communication chann els operating up to 224 Gbps per lane.\n\nSpeaker(s): David Keezer\, \n\nR oom: MCLD 3038\, Bldg: MacLeod Building\, 2356 Main Mall\, Vancouver\, Bri tish Columbia\, Canada\, V6T 1Z4 LOCATION:Room: MCLD 3038\, Bldg: MacLeod Building\, 2356 Main Mall\, Vancou ver\, British Columbia\, Canada\, V6T 1Z4 ORGANIZER:shahriar@ece.ubc.ca SEQUENCE:21 SUMMARY:Adaptable FPGA-based Test Development Platform for Next Generation ICs URL;VALUE=URI:https://events.vtools.ieee.org/m/557548 X-ALT-DESC:Description: <br /><p>Technical seminar by Professor David Keeze r\, IEEE Life Fellow\, Chair Professor at EIT\, Ningbo</p>\n<p class="MsoN ormal"><span lang="EN-US">Today&rsquo\;s integrated circuits may contain b illions of transistors and operate at multiple gigahertz clock rates.&nbsp \; The communication port input and output aggregate bandwidths can easily exceed a terahertz (e.g. 800G and 1.6T PCIe and fiber-optic ports).&nbsp\ ; Furthermore\, some ICs support multiple high-speed communication ports a s well as high-performance analog/RF signals. All these critical features need precise testing to ensure product quality.&nbsp\; While existing auto mated test equipment (ATE) can handle the bulk of &ldquo\;mainstream&rdquo \; IC test requirements\, they are not well-suited for these most advanced applications and are not easily adapted to new test challenges of future devices that may use entirely new signaling protocols.&nbsp\;&nbsp\; There is therefore a &ldquo\;gap&rdquo\; between the ability of ATE and the tes t needs of the most advanced devices.&nbsp\; To address this problem\, we are assembling an FPGA-based test-development platform that can quickly ad apt to future test requirements.&nbsp\; This presentation will describe th e strategy and system architecture and show some early demonstrations for testing mixed analog/digital ICs as well as communication channels operati ng up to 224 Gbps per lane.</span></p>\n<p>&nbsp\;</p> END:VEVENT END:VCALENDAR