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PRODID:IEEE vTools.Events//EN
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DTSTART:20260308T030000
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DTSTART:20261101T010000
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BEGIN:VEVENT
DTSTAMP:20260428T201719Z
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DTSTART;TZID=America/Los_Angeles:20260501T100000
DTEND;TZID=America/Los_Angeles:20260501T111500
DESCRIPTION:Despite the much-debated end of Moore's Law\, CMOS scaling stil
 l maintains economic relevance with 2nm gate-all-around SoCs (Intel 18A) a
 lready in high-volume manufacturing since January 2026. Area scaling exten
 sively driven by design/technology innovations co-optimized for primarily 
 logic scaling continues to offer compelling node-to-node power\, performan
 ce\, area\, and cost benefits. In this tutorial\, we will start with a wal
 k through memory lane\, recounting a brief history of transistor evolution
  to motivate the migration from the planar MOSFET to the fully depleted Fi
 nFET. We will summarize the key process technology elements that have enab
 led the finFET CMOS nodes\, highlighting the resulting technology characte
 ristics and challenges. This will set the stage for transitioning to the n
 anoribbon gate-all-around device architecture and unveiling the magic of h
 ow these devices are fabricated.\n\nSpeaker(s): Alvin Loke\, \n\nVirtual: 
 https://events.vtools.ieee.org/m/557633
LOCATION:Virtual: https://events.vtools.ieee.org/m/557633
ORGANIZER:zahra.najafi@csus.edu
SEQUENCE:10
SUMMARY:The Road to Gate- All-Around CMOS
URL;VALUE=URI:https://events.vtools.ieee.org/m/557633
X-ALT-DESC:Description: <br /><p class="p1">Despite the much-debated end of
  Moore's Law\, CMOS scaling still maintains economic relevance with 2nm ga
 te-all-around SoCs (Intel 18A) already in high-volume manufacturing since 
 January 2026. Area scaling extensively driven by design/technology innovat
 ions co-optimized for primarily logic scaling continues to offer compellin
 g node-to-node power\, performance\, area\, and cost benefits. In this tut
 orial\, we will start with a walk through memory lane\, recounting a brief
  history of transistor evolution to motivate the migration from the planar
  MOSFET to the fully depleted FinFET. We will summarize the key process te
 chnology elements that have enabled the finFET CMOS nodes\, highlighting t
 he resulting technology characteristics and challenges. This will set the 
 stage for transitioning to the nanoribbon gate-all-around device architect
 ure and unveiling the&nbsp\;magic of how these devices are fabricated.</p>
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