BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:Europe/London BEGIN:DAYLIGHT DTSTART:20260329T020000 TZOFFSETFROM:+0000 TZOFFSETTO:+0100 RRULE:FREQ=YEARLY;BYDAY=-1SU;BYMONTH=3 TZNAME:BST END:DAYLIGHT BEGIN:STANDARD DTSTART:20261025T010000 TZOFFSETFROM:+0100 TZOFFSETTO:+0000 RRULE:FREQ=YEARLY;BYDAY=-1SU;BYMONTH=10 TZNAME:GMT END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20260518T084001Z UID:77C35FC7-EC94-4FB9-94D3-9A2D34AC8926 DTSTART;TZID=Europe/London:20260629T110000 DTEND;TZID=Europe/London:20260630T140000 DESCRIPTION:This intensive two-day bootcamp brings together students\, engi neers\, and enthusiasts from all backgrounds to explore the world of custo m silicon design. No prior IC design experience is required.\n\nParticipan ts will be guided from the fundamentals of how transistors behave all the way through to the generation of a GDSII layout file ready for fabrication \, following the same process used in Tiny Tapeout. Tiny tapeout is the op en-source community shuttle program that has already sent hundreds of cust om designs to a real chip foundry.\n\nAgenda: \nDay 1: Circuits and HDL In troduction\n\nThe first day begins with an accessible introduction to IC d esign and the landscape of open-source tooling that has transformed what i s possible outside of industry. Morning sessions cover transistor-level ci rcuit design: how MOSFETs switch\, how simple gates are constructed\, and how basic analogue and digital building blocks are characterised through s imulation. Attendees will work through guided workshop exercises using ope n-source SPICE-compatible tools\, measuring key parameters and building in tuition for the relationship between physical device behaviour and circuit performance.\n\nThe afternoon transitions to hardware description languag es\, where participants will write and simulate digital logic in HDL\, lea rning how behavioural and structural descriptions translate into synthesiz able circuits. Workshop exercises progress from simple combinational block s through to small sequential designs\, giving everyone practical experien ce with the design entry process used in modern digital flows.\n\nDay 2: W orkshops & ASIC workflow\n\nDay two is dedicated to the complete ASIC flow . The morning sessions explain the Tiny Tapeout project in depth : how the shuttle model works\, how individual designs are stitched into a shared d ie\, and what happens between design submission and receiving a packaged c hip. Attendees will then work through the full tapeout workflow hands-on: taking an HDL design through synthesis\, floorplanning\, place and route\, design rule checking\, and final GDS generation using the OpenLane flow. Each stage of the physical design process is explained in context\, so par ticipants leave understanding not just how to run the tools but why each s tep exists.\n\nThe day closes with a discussion of next steps: how to subm it a design to an upcoming Tiny Tapeout shuttle\, how to get involved with the broader open silicon community\, and resources for continuing the jou rney into analogue design\, custom standard cells\, and beyond.\n\nBldg: M alet Place Engineering Building\, Sir Eric Ash Laboratory\, University Col lege London\, London\, England\, United Kingdom LOCATION:Bldg: Malet Place Engineering Building\, Sir Eric Ash Laboratory\, University College London\, London\, England\, United Kingdom ORGANIZER:seerat.sekhon.23@ucl.ac.uk SEQUENCE:34 SUMMARY:UCL IEEE CASS Bootcamp — Designing Silicon from First Principles URL;VALUE=URI:https://events.vtools.ieee.org/m/558033 X-ALT-DESC:Description: <br /><p>This intensive two-day bootcamp brings tog ether students\, engineers\, and enthusiasts from all backgrounds to explo re the world of custom silicon design. No prior IC design experience is re quired.</p>\n<p>Participants will be guided from the fundamentals of how t ransistors behave all the way through to the generation of a GDSII layout file ready for fabrication\, following the same process used in Tiny Tapeo ut. Tiny tapeout is the open-source community shuttle program that has alr eady sent hundreds of custom designs to a real chip foundry.</p>\n<p>&nbsp \;</p>\n<p>&nbsp\;</p><br /><br />Agenda: <br /><p><strong>Day 1: &nbsp\;C ircuits and HDL Introduction</strong></p>\n<p>The first day begins with an accessible introduction to IC design and the landscape of open-source too ling that has transformed what is possible outside of industry. Morning se ssions cover transistor-level circuit design: how MOSFETs switch\, how sim ple gates are constructed\, and how basic analogue and digital building bl ocks are characterised through simulation. Attendees will work through gui ded workshop exercises using open-source SPICE-compatible tools\, measurin g key parameters and building intuition for the relationship between physi cal device behaviour and circuit performance.</p>\n<p>The afternoon transi tions to hardware description languages\, where participants will write an d simulate digital logic in HDL\, learning how behavioural and structural descriptions translate into synthesizable circuits. Workshop exercises pro gress from simple combinational blocks through to small sequential designs \, giving everyone practical experience with the design entry process used in modern digital flows.</p>\n<p><strong>Day 2: Workshops &amp\; ASIC </s trong><strong>workflow</strong></p>\n<p>Day two is dedicated to the comple te ASIC flow. The morning sessions explain the Tiny Tapeout project in dep th : how the shuttle model works\, how individual designs are stitched int o a shared die\, and what happens between design submission and receiving a packaged chip. Attendees will then work through the full tapeout workflo w hands-on: taking an HDL design through synthesis\, floorplanning\, place and route\, design rule checking\, and final GDS generation using the Ope nLane flow. Each stage of the physical design process is explained in cont ext\, so participants leave understanding not just how to run the tools bu t why each step exists.</p>\n<p>The day closes with a discussion of next s teps: how to submit a design to an upcoming Tiny Tapeout shuttle\, how to get involved with the broader open silicon community\, and resources for c ontinuing the journey into analogue design\, custom standard cells\, and b eyond.</p> END:VEVENT END:VCALENDAR