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DTSTART:20260308T030000
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DTSTART:20261101T010000
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DTSTAMP:20260514T142458Z
UID:88B59B57-8138-4996-A721-9EE18A46A773
DTSTART;TZID=America/New_York:20260507T080000
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DESCRIPTION:Event Details:\n\nDate: May 7\n\nTime: 8:00 AM – 10:00 AM\n\n
 Location: A.V. Williams Building\, Room 1146\n\nUniversity of Maryland\, C
 ollege Park\n\nDirections: https://maps.app.goo.gl/pgmdyGqYJyHwvcxX8\n\nTh
 e session will feature a variety of projects covering both analog and digi
 tal circuit design. Some\n\nof these projects will be fabricated in TSMC
 ’s 180nm CMOS process\, providing insight into real\n\nsilicon implement
 ations.\n\nThis is a great opportunity to interact with students\, explore
  innovative designs\, and engage with\n\nthe mixed-signal VLSI community.\
 n\nIf you need more information\, please reach out to:\n\nDr. Sahil Shah\n
 \nsshah389@umd.edu\n\nAgenda: \nPoster Session\n\nRoom: 1146\, Bldg: A.V W
 illiams\, 8223 Paint Branch Dr\, College Park\, University of Maryland\, C
 ollege Park\, College Park\, Maryland\, United States\, 20740
LOCATION:Room: 1146\, Bldg: A.V Williams\, 8223 Paint Branch Dr\, College P
 ark\, University of Maryland\, College Park\, College Park\, Maryland\, Un
 ited States\, 20740
ORGANIZER:sshah389@umd.edu
SEQUENCE:7
SUMMARY:ENEE 408D/719M Mixed-Signal VLSI Capstone Poster Session
URL;VALUE=URI:https://events.vtools.ieee.org/m/558597
X-ALT-DESC:Description: &lt;br /&gt;&lt;p&gt;&lt;em&gt;Event Details:&lt;/em&gt;&lt;/p&gt;\n&lt;p&gt;&lt;em&gt;Date: 
 May 7&lt;/em&gt;&lt;/p&gt;\n&lt;p&gt;&lt;em&gt;Time: 8:00 AM &amp;ndash\; 10:00 AM&lt;/em&gt;&lt;/p&gt;\n&lt;p&gt;&lt;em&gt;Lo
 cation: A.V. Williams Building\, Room 1146&lt;/em&gt;&lt;/p&gt;\n&lt;p&gt;&lt;em&gt;University of 
 Maryland\, College Park&lt;/em&gt;&lt;/p&gt;\n&lt;p&gt;&lt;em&gt;Directions: https://maps.app.goo.
 gl/pgmdyGqYJyHwvcxX8&lt;/em&gt;&lt;/p&gt;\n&lt;p&gt;&lt;em&gt;The session will feature a variety o
 f projects covering both analog and digital circuit design. Some&lt;/em&gt;&lt;/p&gt;\
 n&lt;p&gt;&lt;em&gt;of these projects will be fabricated in TSMC&amp;rsquo\;s 180nm CMOS p
 rocess\, providing insight into real&lt;/em&gt;&lt;/p&gt;\n&lt;p&gt;&lt;em&gt;silicon implementati
 ons.&lt;/em&gt;&lt;/p&gt;\n&lt;p&gt;&lt;em&gt;This is a great opportunity to interact with student
 s\, explore innovative designs\, and engage with&lt;/em&gt;&lt;/p&gt;\n&lt;p&gt;&lt;em&gt;the mixe
 d-signal VLSI community.&lt;/em&gt;&lt;/p&gt;\n&lt;p&gt;&lt;em&gt;If you need more information\, p
 lease reach out to:&lt;/em&gt;&lt;/p&gt;\n&lt;p&gt;&lt;em&gt;Dr. Sahil Shah&lt;/em&gt;&lt;/p&gt;\n&lt;p&gt;&lt;em&gt;sshah
 389@umd.edu&lt;/em&gt;&lt;/p&gt;&lt;br /&gt;&lt;br /&gt;Agenda: &lt;br /&gt;&lt;p&gt;Poster Session&amp;nbsp\;&lt;/p&gt;
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