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VERSION:2.0
PRODID:IEEE vTools.Events//EN
CALSCALE:GREGORIAN
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TZID:Asia/Kolkata
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DTSTART:19451014T230000
TZOFFSETFROM:+0630
TZOFFSETTO:+0530
TZNAME:IST
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BEGIN:VEVENT
DTSTAMP:20260516T070909Z
UID:CCCB4E48-AA07-4A8F-8877-7AE4CDDE05BA
DTSTART;TZID=Asia/Kolkata:20260530T200000
DTEND;TZID=Asia/Kolkata:20260530T210000
DESCRIPTION:The IEEE CEDA Bangalore Chapter proudly presents Episode 5 of t
 he Industry Insights Series\, featuring an expert session on Clock Generat
 ors and Timing Circuits used in modern semiconductor and VLSI systems.\n\n
 This webinar will provide an industry-oriented introduction to:\n\n- Phase
  Locked Loops (PLL)\n- Delay Locked Loops (DLL)\n- Clock generation and sy
 nchronization\n- Timing challenges in high-speed digital systems\n- Applic
 ations in SoCs\, processors\, communication systems\, and mixed-signal ICs
 \n- Real-world design insights from the semiconductor industry\n\nThe sess
 ion is designed for:\n\n- Students interested in VLSI and semiconductor de
 sign\n- Early-career engineers\n- Researchers and academicians\n- Industry
  professionals looking to strengthen fundamentals in timing architecture\n
 \n[]\n\nSpeaker(s): Pradeep Anantula\n\nVirtual: https://events.vtools.iee
 e.org/m/560036
LOCATION:Virtual: https://events.vtools.ieee.org/m/560036
ORGANIZER:avamsikrishna@ieee.org
SEQUENCE:9
SUMMARY:IEEE CEDA Industry Insights Series – Episode 5 : Explore the Worl
 d of Clock Generators (PLL\, DLL)
URL;VALUE=URI:https://events.vtools.ieee.org/m/560036
X-ALT-DESC:Description: &lt;br /&gt;&lt;p data-start=&quot;216&quot; data-end=&quot;428&quot;&gt;The IEEE C
 EDA Bangalore Chapter proudly presents Episode 5 of the &lt;em data-start=&quot;28
 2&quot; data-end=&quot;308&quot;&gt;Industry Insights Series&lt;/em&gt;\, featuring an expert sess
 ion on &lt;strong data-start=&quot;341&quot; data-end=&quot;381&quot;&gt;Clock Generators and Timing
  Circuits&lt;/strong&gt; used in modern semiconductor and VLSI systems.&lt;/p&gt;\n&lt;p 
 data-start=&quot;430&quot; data-end=&quot;493&quot;&gt;This webinar will provide an industry-orie
 nted introduction to:&lt;/p&gt;\n&lt;ul data-start=&quot;495&quot; data-end=&quot;778&quot;&gt;\n&lt;li data-
 section-id=&quot;3whf6b&quot; data-start=&quot;495&quot; data-end=&quot;521&quot;&gt;Phase Locked Loops (PL
 L)&lt;/li&gt;\n&lt;li data-section-id=&quot;hngykd&quot; data-start=&quot;522&quot; data-end=&quot;548&quot;&gt;Dela
 y Locked Loops (DLL)&lt;/li&gt;\n&lt;li data-section-id=&quot;19k9an3&quot; data-start=&quot;549&quot; 
 data-end=&quot;587&quot;&gt;Clock generation and synchronization&lt;/li&gt;\n&lt;li data-section
 -id=&quot;1plzpbb&quot; data-start=&quot;588&quot; data-end=&quot;637&quot;&gt;Timing challenges in high-sp
 eed digital systems&lt;/li&gt;\n&lt;li data-section-id=&quot;sx30mh&quot; data-start=&quot;638&quot; da
 ta-end=&quot;717&quot;&gt;Applications in SoCs\, processors\, communication systems\, a
 nd mixed-signal ICs&lt;/li&gt;\n&lt;li data-section-id=&quot;1p8fitg&quot; data-start=&quot;718&quot; d
 ata-end=&quot;778&quot;&gt;Real-world design insights from the semiconductor industry&lt;/
 li&gt;\n&lt;/ul&gt;\n&lt;p data-start=&quot;780&quot; data-end=&quot;808&quot;&gt;The session is designed for
 :&lt;/p&gt;\n&lt;ul data-start=&quot;809&quot; data-end=&quot;1002&quot;&gt;\n&lt;li data-section-id=&quot;vn1pxc&quot;
  data-start=&quot;809&quot; data-end=&quot;863&quot;&gt;Students interested in VLSI and semicondu
 ctor design&lt;/li&gt;\n&lt;li data-section-id=&quot;1mbiiha&quot; data-start=&quot;864&quot; data-end=
 &quot;888&quot;&gt;Early-career engineers&lt;/li&gt;\n&lt;li data-section-id=&quot;15lokry&quot; data-star
 t=&quot;889&quot; data-end=&quot;919&quot;&gt;Researchers and academicians&lt;/li&gt;\n&lt;li data-section
 -id=&quot;30n73i&quot; data-start=&quot;920&quot; data-end=&quot;1002&quot;&gt;Industry professionals looki
 ng to strengthen fundamentals in timing architecture&lt;/li&gt;\n&lt;/ul&gt;\n&lt;p style
 =&quot;text-align: center\;&quot;&gt;&lt;img src=&quot;https://events.vtools.ieee.org/vtools_ui
 /media/display/9a450235-cfc2-4de2-838f-3ecd969c32a6&quot; alt=&quot;&quot; width=&quot;500&quot; he
 ight=&quot;625&quot;&gt;&lt;/p&gt;
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