BEGIN:VCALENDAR
VERSION:2.0
PRODID:IEEE vTools.Events//EN
CALSCALE:GREGORIAN
BEGIN:VTIMEZONE
TZID:Asia/Kolkata
BEGIN:STANDARD
DTSTART:19451014T230000
TZOFFSETFROM:+0630
TZOFFSETTO:+0530
TZNAME:IST
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20260709T031821Z
UID:56B87889-1774-46FA-9B79-C4156938B327
DTSTART;TZID=Asia/Kolkata:20260611T090000
DTEND;TZID=Asia/Kolkata:20260611T170000
DESCRIPTION:The event “Hardware Design Thinking” was successfully organ
 ized on 11 June 2026 at Sai Vidya Institute of Technology\, Bengaluru by S
 ai Vidya Institute of Technology in association with the Institution’s I
 nnovation Council (IIC)\, IEEE CEDA Bangalore Chapter\, and IEEE Bangalore
  Section. The workshop was designed to provide students with practical exp
 osure to hardware architecture problem-solving\, system-level reasoning\, 
 design trade-offs\, and engineering thought processes that go beyond conve
 ntional RTL-based learning. The event aimed to help students understand ho
 w hardware engineers approach real-world silicon challenges\, analyze arch
 itectural problems\, and defend design decisions through structured techni
 cal reasoning.\n\n[]	[]	[]\n[]	[]	[]\n\nSpeaker(s): Milind Parelkar\, Pala
 sh Khandale\n\nSai Vidya Institute of Technology\, 5H95+CP2\, via\, Yelaha
 nka\, Rajanukunte\, Bengaluru\, Karnataka\, India\, 560119
LOCATION:Sai Vidya Institute of Technology\, 5H95+CP2\, via\, Yelahanka\, R
 ajanukunte\, Bengaluru\, Karnataka\, India\, 560119
ORGANIZER:avamsikrishna@ieee.org
SEQUENCE:5
SUMMARY:Hardware Design Thinking Workshop
URL;VALUE=URI:https://events.vtools.ieee.org/m/560127
X-ALT-DESC:Description: &lt;br /&gt;&lt;p style=&quot;text-align: justify\;&quot;&gt;&lt;span lang=&quot;
 EN-US&quot; style=&quot;font-size: 13.0pt\; font-family: &#39;Calibri&#39;\,sans-serif\; mso
 -ascii-theme-font: major-latin\; mso-hansi-theme-font: major-latin\; mso-b
 idi-theme-font: major-latin\;&quot;&gt;The event &lt;strong&gt;&lt;span style=&quot;font-family:
  &#39;Calibri&#39;\,sans-serif\; mso-ascii-theme-font: major-latin\; mso-hansi-the
 me-font: major-latin\; mso-bidi-theme-font: major-latin\;&quot;&gt;&amp;ldquo\;Hardwar
 e Design Thinking&amp;rdquo\;&lt;/span&gt;&lt;/strong&gt; was successfully organized on &lt;s
 trong&gt;&lt;span style=&quot;font-family: &#39;Calibri&#39;\,sans-serif\; mso-ascii-theme-fo
 nt: major-latin\; mso-hansi-theme-font: major-latin\; mso-bidi-theme-font:
  major-latin\;&quot;&gt;11 June 2026&lt;/span&gt;&lt;/strong&gt; at &lt;strong&gt;&lt;span style=&quot;font-
 family: &#39;Calibri&#39;\,sans-serif\; mso-ascii-theme-font: major-latin\; mso-ha
 nsi-theme-font: major-latin\; mso-bidi-theme-font: major-latin\;&quot;&gt;Sai Vidy
 a Institute of Technology\, Bengaluru&lt;/span&gt;&lt;/strong&gt; by &lt;strong&gt;&lt;span sty
 le=&quot;font-family: &#39;Calibri&#39;\,sans-serif\; mso-ascii-theme-font: major-latin
 \; mso-hansi-theme-font: major-latin\; mso-bidi-theme-font: major-latin\;&quot;
 &gt;Sai Vidya Institute of Technology&lt;/span&gt;&lt;/strong&gt; in association with the
  &lt;strong&gt;&lt;span style=&quot;font-family: &#39;Calibri&#39;\,sans-serif\; mso-ascii-theme
 -font: major-latin\; mso-hansi-theme-font: major-latin\; mso-bidi-theme-fo
 nt: major-latin\;&quot;&gt;Institution&amp;rsquo\;s Innovation Council (IIC)\, IEEE CE
 DA Bangalore Chapter\, and IEEE Bangalore Section&lt;/span&gt;&lt;/strong&gt;. The wor
 kshop was designed to provide students with practical exposure to &lt;strong&gt;
 &lt;span style=&quot;font-family: &#39;Calibri&#39;\,sans-serif\; mso-ascii-theme-font: ma
 jor-latin\; mso-hansi-theme-font: major-latin\; mso-bidi-theme-font: major
 -latin\;&quot;&gt;hardware architecture problem-solving\, system-level reasoning\,
  design trade-offs\, and engineering thought processes&lt;/span&gt;&lt;/strong&gt; tha
 t go beyond conventional RTL-based learning. The event aimed to help stude
 nts understand how hardware engineers approach real-world silicon challeng
 es\, analyze architectural problems\, and defend design decisions through 
 structured technical reasoning.&lt;/span&gt;&lt;/p&gt;\n&lt;table style=&quot;border-collapse:
  collapse\; width: 100%\;&quot; border=&quot;1&quot;&gt;&lt;colgroup&gt;&lt;col style=&quot;width: 33.3009
 %\;&quot;&gt;&lt;col style=&quot;width: 33.3009%\;&quot;&gt;&lt;col style=&quot;width: 33.3009%\;&quot;&gt;&lt;/colgr
 oup&gt;\n&lt;tbody&gt;\n&lt;tr&gt;\n&lt;td style=&quot;text-align: center\;&quot;&gt;&lt;img src=&quot;https://ev
 ents.vtools.ieee.org/vtools_ui/media/display/8eb1bf4c-d57f-4161-853b-95418
 8a43796&quot; alt=&quot;&quot; width=&quot;300&quot; height=&quot;219&quot;&gt;&lt;/td&gt;\n&lt;td style=&quot;text-align: cen
 ter\;&quot;&gt;&lt;img src=&quot;https://events.vtools.ieee.org/vtools_ui/media/display/02
 c8048e-71c4-430b-a82b-250eecc6a087&quot; alt=&quot;&quot; width=&quot;300&quot; height=&quot;225&quot;&gt;&lt;/td&gt;\
 n&lt;td style=&quot;text-align: center\;&quot;&gt;&lt;img src=&quot;https://events.vtools.ieee.org
 /vtools_ui/media/display/cde46a20-3318-4196-983f-9d1e3e37fba8&quot; alt=&quot;&quot; widt
 h=&quot;300&quot; height=&quot;225&quot;&gt;&lt;/td&gt;\n&lt;/tr&gt;\n&lt;tr&gt;\n&lt;td style=&quot;text-align: center\;&quot;&gt;
 &lt;img src=&quot;https://events.vtools.ieee.org/vtools_ui/media/display/ab6872b6-
 ce00-4765-ac9d-b56e443a370e&quot; alt=&quot;&quot; width=&quot;300&quot; height=&quot;225&quot;&gt;&lt;/td&gt;\n&lt;td st
 yle=&quot;text-align: center\;&quot;&gt;&lt;img src=&quot;https://events.vtools.ieee.org/vtools
 _ui/media/display/3a1bdde7-0a08-402f-98c3-38177313a41c&quot; alt=&quot;&quot; width=&quot;300&quot;
  height=&quot;225&quot;&gt;&lt;/td&gt;\n&lt;td style=&quot;text-align: center\;&quot;&gt;&lt;img src=&quot;https://ev
 ents.vtools.ieee.org/vtools_ui/media/display/842c04d6-6db1-403d-b0da-8209c
 bf5d2d8&quot; alt=&quot;&quot; width=&quot;300&quot; height=&quot;225&quot;&gt;&lt;/td&gt;\n&lt;/tr&gt;\n&lt;/tbody&gt;\n&lt;/table&gt;
END:VEVENT
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