BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:Asia/Kolkata BEGIN:STANDARD DTSTART:19451014T230000 TZOFFSETFROM:+0630 TZOFFSETTO:+0530 TZNAME:IST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20260517T031226Z UID:56B87889-1774-46FA-9B79-C4156938B327 DTSTART;TZID=Asia/Kolkata:20260611T090000 DTEND;TZID=Asia/Kolkata:20260611T170000 DESCRIPTION:IEEE CEDA Bangalore Chapter\, in association with Sai Vidya Ins titute of Technology\, are organizing a Hardware Design Thinking Workshop aimed at students and early-career professionals interested in digital har dware design and architecture.\n\nThis hands-on\, problem-driven workshop focuses on real-world hardware design challenges through waveform analysis \, block-diagram thinking\, and practical digital design exercises. Partic ipants will explore concepts such as FSMs\, counters\, flip-flops\, logic gates\, synchronous pipelines\, and flow control methodologies while learn ing how hidden design assumptions can lead to silicon bugs.\n\nThe worksho p will be conducted by industry experts:\n\n- Milind Parelkar — Principa l Engineer\, Qualcomm\n- Palash Khandale — Staff Engineer\, ARM\n\nWorks hop Highlights\n\n- Hands-on learning with real-world hardware design scen arios\n- Interactive waveform drawing and timing analysis sessions\n- Prac tical design exercises using FSMs and sequential logic\n- Architecture-foc used problem solving and design thinking\n- Collaborative discussions\, wh iteboard sessions\, and Q&A\n\nSpeaker(s): Milind Parelkar\, Palash Khanda le\n\nSai Vidya Institute of Technology\, 5H95+CP2\, via\, Yelahanka\, Raj anukunte\, Bengaluru\, Karnataka\, India\, 560119 LOCATION:Sai Vidya Institute of Technology\, 5H95+CP2\, via\, Yelahanka\, R ajanukunte\, Bengaluru\, Karnataka\, India\, 560119 ORGANIZER:avamsikrishna@ieee.org SEQUENCE:3 SUMMARY:Hardware Design Thinking Workshop URL;VALUE=URI:https://events.vtools.ieee.org/m/560127 X-ALT-DESC:Description: <br /><p data-start="37" data-end="311">IEEE CEDA B angalore Chapter\, in association with Sai Vidya Institute of Technology\, are organizing a&nbsp\;<strong data-start="169" data-end="206">Hardware D esign Thinking Workshop</strong> aimed at students and early-career profes sionals interested in digital hardware design and architecture.</p>\n<p da ta-start="313" data-end="700">This hands-on\, problem-driven workshop focu ses on real-world hardware design challenges through waveform analysis\, b lock-diagram thinking\, and practical digital design exercises. Participan ts will explore concepts such as FSMs\, counters\, flip-flops\, logic gate s\, synchronous pipelines\, and flow control methodologies while learning how hidden design assumptions can lead to silicon bugs.</p>\n<p data-start ="702" data-end="753">The workshop will be conducted by industry experts:< /p>\n<ul data-start="754" data-end="854">\n<li data-section-id="wjib5z" da ta-start="754" data-end="808"><strong data-start="756" data-end="775">Mili nd Parelkar</strong> &mdash\; Principal Engineer\, Qualcomm</li>\n<li data -section-id="1phm0ra" data-start="809" data-end="854"><strong data-start=" 811" data-end="830">Palash Khandale</strong> &mdash\; Staff Engineer\, ARM </li>\n</ul>\n<h3 data-section-id="pehbts" data-start="856" data-end="879" >Workshop Highlights</h3>\n<ul data-start="880" data-end="1189">\n<li data -section-id="1o4zbqe" data-start="880" data-end="943">Hands-on learning wi th real-world hardware design scenarios</li>\n<li data-section-id="8ew0vr" data-start="944" data-end="1005">Interactive waveform drawing and timing analysis sessions</li>\n<li data-section-id="2lx7vx" data-start="1006" dat a-end="1068">Practical design exercises using FSMs and sequential logic</l i>\n<li data-section-id="6vnord" data-start="1069" data-end="1129">Archite cture-focused problem solving and design thinking</li>\n<li data-section-i d="1kkderv" data-start="1130" data-end="1189">Collaborative discussions\, whiteboard sessions\, and Q&amp\;A</li>\n</ul> END:VEVENT END:VCALENDAR