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DESCRIPTION:Formal vs Simulation: When\, Why\, and Where\n\nMuhammed Luqman
  Jukaku\, Synopsys\n\nAbstract: As modern SoCs continue to grow in complex
 ity\, verification teams face increasing pressure to achieve higher qualit
 y\, faster coverage closure\, and shorter time to market. While simulation
  remains the foundation of most verification flows\, formal verification h
 as emerged as a powerful complementary technique for uncovering deep corne
 r case bugs\, proving critical properties\, and improving overall verifica
 tion confidence. Yet many teams still struggle with practical questions: W
 hen should formal be used? Where does simulation scale better? And how can
  both methodologies work together effectively? This talk presents a practi
 cal industry perspective on the strengths\, limitations\, and real world d
 eployment strategies of simulation and formal verification across IP\, sub
 system and SoC environments. The session will also discuss emerging trends
  including AI assisted verification flows\, intelligent coverage analysis\
 , and the evolving role of formal techniques in next generation SoC verifi
 cation.\n\nSpeaker biography: Muhammed Luqman Jukaku is a Principal SoC Ve
 rification Leader with more than 22 years of experience leading verificati
 on activities across IP\, subsystem\, and SoC for complex high performance
  semiconductor designs. He currently works at Synopsys\, where he leads ve
 rification of complex multi-protocol interconnect and subsystem architectu
 res for advanced interface and SoC platforms.\n\nPlease register to allow 
 for proper planning.\nParking structure located at 2585 Augustine Dr. 3-ho
 ur free parking\n\nSpeaker(s): Muhammed\, \n\nAgenda: \n5:30pm: Networking
 \n\n6:00pm: Talk\n\n7:00pm: Event ends\n\n2510 Augustine Dr\, Santa Clara\
 , CA 95054\, Santa Clara\, California\, United States\, 95054
LOCATION:2510 Augustine Dr\, Santa Clara\, CA 95054\, Santa Clara\, Califor
 nia\, United States\, 95054
ORGANIZER:pcaragiulo@ieee.org
SEQUENCE:13
SUMMARY:Formal vs Simulation: When\, Why\, and Where + SSCS Networking Nigh
 t
URL;VALUE=URI:https://events.vtools.ieee.org/m/561660
X-ALT-DESC:Description: &lt;br /&gt;&lt;div&gt;\n&lt;div&gt;\n&lt;table style=&quot;border-collapse: 
 collapse\; width: 100%\; background-color: #ffffff\; border: 1px none #FFF
 FFF\;&quot; border=&quot;1&quot;&gt;&lt;colgroup&gt;&lt;col style=&quot;width: 50%\;&quot;&gt;&lt;col style=&quot;width: 5
 0%\;&quot;&gt;&lt;/colgroup&gt;\n&lt;tbody&gt;\n&lt;tr&gt;\n&lt;td style=&quot;border-color: rgb(255\, 255\,
  255)\;&quot;&gt;\n&lt;p&gt;&lt;strong id=&quot;docs-internal-guid-acd13018-7fff-4eb6-0962-02aec
 b326d9f&quot;&gt;Formal vs Simulation: When\, Why\, and Where&lt;/strong&gt;&lt;/p&gt;\n&lt;p&gt;Muh
 ammed Luqman Jukaku\, Synopsys&lt;/p&gt;\n&lt;/td&gt;\n&lt;td style=&quot;text-align: center\;
  border-color: rgb(255\, 255\, 255)\;&quot;&gt;&lt;strong id=&quot;docs-internal-guid-151c
 353d-7fff-727f-94f0-e0f4aa75a10e&quot;&gt;&lt;img src=&quot;https://events.vtools.ieee.org
 /vtools_ui/media/display/083c49fa-1989-4f18-9b6a-14f03d73f27e&quot; width=&quot;240&quot;
  height=&quot;223&quot;&gt;&lt;/strong&gt;&lt;/td&gt;\n&lt;/tr&gt;\n&lt;/tbody&gt;\n&lt;/table&gt;\n&lt;/div&gt;\n&lt;div&gt;&amp;nbs
 p\;&lt;/div&gt;\n&lt;div&gt;&lt;strong&gt;Abstract: &lt;/strong&gt;As modern SoCs continue to grow
  in complexity\, verification teams face increasing pressure to achieve hi
 gher quality\, faster coverage closure\, and shorter time to market. While
  simulation remains the foundation of most verification flows\, formal ver
 ification has emerged as a powerful complementary technique for uncovering
  deep corner case bugs\, proving critical properties\, and improving overa
 ll verification confidence. Yet many teams still struggle with practical q
 uestions: When should formal be used? Where does simulation scale better? 
 And how can both methodologies work together effectively? This talk presen
 ts a practical industry perspective on the strengths\, limitations\, and r
 eal world deployment strategies of simulation and formal verification acro
 ss IP\, subsystem and SoC environments. The session will also discuss emer
 ging trends including AI assisted verification flows\, intelligent coverag
 e analysis\, and the evolving role of formal techniques in next generation
  SoC verification.&lt;/div&gt;\n&lt;div&gt;&amp;nbsp\;&lt;/div&gt;\n&lt;/div&gt;\n&lt;div&gt;&lt;strong&gt;Speaker
  biography:&lt;/strong&gt; Muhammed Luqman Jukaku is a Principal SoC Verificatio
 n Leader with more than 22 years of experience leading verification activi
 ties across IP\, subsystem\, and SoC for complex high performance semicond
 uctor designs. He currently works at Synopsys\, where he leads verificatio
 n of complex multi-protocol interconnect and subsystem architectures for a
 dvanced interface and SoC platforms.&lt;/div&gt;\n&lt;div&gt;&amp;nbsp\;&lt;/div&gt;\n&lt;div&gt;\n&lt;p&gt;
 Please register to allow for proper planning.&lt;br&gt;Parking structure located
  at 2585 Augustine Dr. &amp;nbsp\;3-hour free parking&lt;/p&gt;\n&lt;/div&gt;&lt;br /&gt;&lt;br /&gt;A
 genda: &lt;br /&gt;&lt;p&gt;5:30pm: Networking&lt;/p&gt;\n&lt;p&gt;6:00pm: Talk&lt;/p&gt;\n&lt;p&gt;7:00pm: Ev
 ent ends&lt;/p&gt;
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