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DTSTART:20260308T030000
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DTSTART:20261101T010000
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BEGIN:VEVENT
DTSTAMP:20260618T202651Z
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DTSTART;TZID=America/Los_Angeles:20260616T163000
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DESCRIPTION:By the end of years 70s\, microprocessors were designed by hand
  showing excellent layout compaction. It will be shown some highlights of 
 the reverse engineering of the Z8000\, which control part was designed by 
 hand\, showing several layout optimization strategies. The observation of 
 the Z8000 layout inspired the research of methods to do the automatic gene
 ration of the layout of any transistor network\, allowing to reduce the nu
 mber of transistors to implement a circuit\, and by consequence\, the leak
 age power. Some of the layout automation tools developed by our group are 
 briefly presented.\n\nSpeaker(s): Ricardo Reis\, \n\nRoom: ASB 10704\, Bld
 g: Applied Science Building \, Simon Fraser University\, Burnaby \, Britis
 h Columbia\, Canada\, V5A 1S6\, Virtual: https://events.vtools.ieee.org/m/
 561894
LOCATION:Room: ASB 10704\, Bldg: Applied Science Building \, Simon Fraser U
 niversity\, Burnaby \, British Columbia\, Canada\, V5A 1S6\, Virtual: http
 s://events.vtools.ieee.org/m/561894
ORGANIZER:zhidali@ieee.org
SEQUENCE:19
SUMMARY:Physical Design: From Past to Future
URL;VALUE=URI:https://events.vtools.ieee.org/m/561894
X-ALT-DESC:Description: <br /><div dir="ltr">By the end of years 70s\, micr
 oprocessors were designed by hand showing excellent layout compaction. It 
 will be shown some highlights of the reverse engineering of the Z8000\, wh
 ich control part was designed by hand\, showing several layout optimizatio
 n strategies. The observation of the Z8000 layout inspired the research of
  methods to do the automatic generation of the layout of any transistor ne
 twork\, allowing to reduce the number of transistors to implement a circui
 t\, and by consequence\, the leakage power. Some of the layout automation 
 tools developed by our group are briefly presented.</div>
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