BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:America/New_York BEGIN:DAYLIGHT DTSTART:20260308T030000 TZOFFSETFROM:-0500 TZOFFSETTO:-0400 RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3 TZNAME:EDT END:DAYLIGHT BEGIN:STANDARD DTSTART:20261101T010000 TZOFFSETFROM:-0400 TZOFFSETTO:-0500 RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11 TZNAME:EST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20260607T181701Z UID:0483AFC3-876D-45C2-8DF2-22BC6DF8EB60 DTSTART;TZID=America/New_York:20260609T170000 DTEND;TZID=America/New_York:20260609T210000 DESCRIPTION:Overview:\n\nThis technical session\, presented by Dr. John U. Knickerbocker\, researcher from IBM\, will provide a high-level overview o f the latest developments in semiconductor and advanced packaging technolo gies\, including chiplets\, heterogeneous integration\, wafer-scale packag ing\, co-packaged optics/photonics\, thermal management\, reliability test ing\, and advanced manufacturing processes. The presentation will explore how next-generation architectures\, co-design methodologies\, and advanced packaging innovations are accelerating system performance\, improving ene rgy efficiency\, and enabling the transition from prototype development to high-volume manufacturing across the electronics industry.\n\n- IBM Semic onductor & Advanced Packaging Research\n- What’s next in Systems\n- Appl ications & Research Ecosystem: Next Generation Innovations\; Prototype to Volume Manufacturing\n\n- Architecture\, EDA and Co-Design\n- Application form factor / Specifications: System Performance\, Energy Efficiency\, … \n- Digital Simulations and Advanced Test Vehicle Co-Design / Product Desi gn Kit – (PDK)\n\n- Chiplets\, Packaging\, Components fabrication and Te st\n- Test Vehicle fabrication\n- Component inspection and test\n\n- Chipl et and Advanced Packaging Integration\n- Test Vehicle Assembly / Integrati on\n- Short loop iterations equipment / process development and characteri zation\n\n- Modules\, Wafer Scale Integration\, Thermal Solutions\, Co-Pac kaged Optics / Photonics and Characterization\n- Power delivery\, thermal solutions\, electrical and optical interconnections\, Integration Compatib ility\n- Module / Board level iterations equipment / assembly processes an d characterization / Assembly Design Kit (ADK)\n\n- Reliability\, Test\, C haracterization and Qualifications\n- Reliability Testing / Characterizati on\; Failure Modes\, corrective adjustments from components through integr ation\n- Component through integration\, Stress Test & Compatibility to Ap plication level / JEDEC stress testing\n\n- Summary\n- Chiplet & Advanced Packaging can help accelerate new systems\n- Innovations continue to suppo rt product differentiation\, performance and energy efficiency\n“IEEE Lo ng Island section members are advised to attend this event at their person al choice and discretion and any fees or other expense paid by LI section members to attend this event will not be reimbursed by section or chapters of LI Section\n\nCo-sponsored by: SMTA\n\nAgenda: \nAgenda:\n\n5:00 pm - Networking Reception (Open Bar)\n\n6:15 pm - Dinner\, Presentation to Foll ow\n\n9:00 pm - Adjourn\n\nRadisson Hotel \, 110 Vanderbilt Motor Parkway\ , Hauppauge\, New York\, United States LOCATION:Radisson Hotel \, 110 Vanderbilt Motor Parkway\, Hauppauge\, New Y ork\, United States ORGANIZER:TJZanatta@gmail.com SEQUENCE:31 SUMMARY:Long Island Chapter Technical Meeting & Dinner: Chiplet & Advanced Packaging Technologies URL;VALUE=URI:https://events.vtools.ieee.org/m/562224 X-ALT-DESC:Description: <br /><p><strong>Overview:</strong></p>\n<p>This te chnical session\, presented by Dr. John U. Knickerbocker\, researcher from IBM\, will provide a high-level overview of the latest developments in se miconductor and advanced packaging technologies\, including chiplets\, het erogeneous integration\, wafer-scale packaging\, co-packaged optics/photon ics\, thermal management\, reliability testing\, and advanced manufacturin g processes. The presentation will explore how next-generation architectur es\, co-design methodologies\, and advanced packaging innovations are acce lerating system performance\, improving energy efficiency\, and enabling t he transition from prototype development to high-volume manufacturing acro ss the electronics industry.</p>\n<ol>\n<li>IBM Semiconductor &amp\; Advan ced Packaging Research\n<ul>\n<li>What&rsquo\;s next in Systems</li>\n<li> Applications &amp\; Research Ecosystem: Next Generation Innovations\; Prot otype to Volume Manufacturing</li>\n</ul>\n</li>\n<li>Architecture\, EDA a nd Co-Design\n<ul>\n<li>Application form factor / Specifications:&nbsp\; S ystem Performance\, Energy Efficiency\, &hellip\;</li>\n<li>Digital Simula tions and Advanced Test Vehicle Co-Design / Product Design Kit &ndash\; (P DK)</li>\n</ul>\n</li>\n<li>Chiplets\, Packaging\, Components fabrication and Test\n<ul>\n<li>Test Vehicle fabrication</li>\n<li>Component inspectio n and test</li>\n</ul>\n</li>\n<li>Chiplet and Advanced Packaging Integrat ion\n<ul>\n<li>Test Vehicle Assembly / Integration</li>\n<li>Short loop it erations equipment / process development and characterization</li>\n</ul>\ n</li>\n<li>Modules\, Wafer Scale Integration\, Thermal Solutions\, Co-Pac kaged Optics / Photonics and Characterization\n<ul>\n<li>Power delivery\, thermal solutions\, electrical and optical interconnections\, Integration Compatibility</li>\n<li>Module / Board level iterations equipment / assemb ly processes and characterization / Assembly Design Kit (ADK)</li>\n</ul>\ n</li>\n<li>Reliability\, Test\, Characterization and Qualifications\n<ul> \n<li>Reliability Testing / Characterization\; Failure Modes\, corrective adjustments from components through integration</li>\n<li>Component throug h integration\, Stress Test &amp\; Compatibility to Application level / JE DEC stress testing</li>\n</ul>\n</li>\n<li>Summary\n<ul>\n<li>Chiplet &amp \; Advanced Packaging can help accelerate new systems</li>\n<li>Innovation s continue to support product differentiation\, performance and energy eff iciency\n<p>&ldquo\;IEEE Long Island section members are advised to attend this event at their personal choice and discretion and any fees or other expense paid by LI section members to attend this event will not be reimbu rsed by section or chapters of LI Section</p>\n</li>\n</ul>\n</li>\n</ol>< br /><br />Agenda: <br /><p><strong>Agenda:</strong></p>\n<p>5:00 pm - Net working Reception (Open Bar)</p>\n<p>6:15 pm - Dinner\, Presentation to Fo llow</p>\n<p>9:00 pm - Adjourn</p>\n<p>&nbsp\;</p> END:VEVENT END:VCALENDAR