BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:America/New_York BEGIN:DAYLIGHT DTSTART:20260308T030000 TZOFFSETFROM:-0500 TZOFFSETTO:-0400 RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3 TZNAME:EDT END:DAYLIGHT BEGIN:STANDARD DTSTART:20261101T010000 TZOFFSETFROM:-0400 TZOFFSETTO:-0500 RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11 TZNAME:EST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20260612T151144Z UID:5965EE1D-BBF9-4FAB-B9DA-D2C4240E1F56 DTSTART;TZID=America/New_York:20260622T173000 DTEND;TZID=America/New_York:20260622T200000 DESCRIPTION:High-tech applications like autonomous driving\, 5G communicati on\, and especially artificial intelligence and machine learning are drivi ng the semiconductor industry to increase microchip complexity and process ing power more than ever. At the same time\, Moore’s Law\, which postula tes that the number of transistors in an integrated circuit doubles every two years and has roughly held since 1975\, is nearing its physical limit. As a result\, the electronics industry has moved towards advanced packagi ng solutions in the past decade.\n\nBroadly\, advanced packaging refers to incorporating multiple chips within a single electronic component\, often utilizing heterogeneous integration\, meaning the different chips within the package have different functions. Additionally\, advanced packaging ty pically includes some degree of vertical stacking among the multiple chips . Stacked structures reduce interconnect length by orders of magnitude\, l eading to higher bandwidths\, capacities\, and data rates.\n\nWhile these stacked features are extremely powerful from an electrical perspective\, t hey are also extremely complex from a structural and material perspective. A single advanced package will often include silicon chips\, a silicon or glass interposer\, and a glass fiber-reinforced organic substrate all att ached to each other with various solder and copper interconnects. The tota l interconnect count can easily be in the hundreds of thousands\, and the smallest interconnects can scale down several orders of magnitude from the overall package size. The whole package may then be covered with a protec tive polymer overmold or utilize a copper or steel stiffener or lid.\n\nTh ese packages require complex fabrication processes involving several high- temperature events like multiple solder reflows\, copper interconnect anne aling\, and polymer cures. The variation in Young’s Modulus and coeffici ent of thermal expansion (CTE) throughout the structure can create stress concentrations that fracture interconnects across dissimilar materials dur ing these many manufacturing-related temperature excursions. Furthermore\, even if the advanced package can be fabricated completely without issue\, soldering it to a circuit board presents a potential problem. The CTE mis matches within the package can warp the package enough to create soldering defects during board-level reflow.\n\nThe rapidly evolving nature of adva nced packaging\, the extreme number of interconnects within a single packa ge\, and the high production cost of cutting-edge semiconductors demand th at simulation play a role in evaluating the manufacturability of novel adv anced package designs. This presentation will overview key manufacturing p rocesses that can be evaluated with thermomechanical FEA for an advanced p ackage design. It will also investigate strategies for dealing with modeli ng complications specific to advanced packages\, including how to address interconnect scaling issues with layer simplification and submodeling and when to consider temperature-dependent and nonlinear material properties.\ n\nSpeaker(s): Tyler\n\nAgenda: \n-\n\n5:30 - 6:00 pm Gather and introduct ions\n6:00 - 6:45 pm Ansys lab tour and electronics capabilities overview\ n6:45 - 7:30 pm Ansys speaker presentation\n7:30 pm Wrap-up\n\nRoom: Suite 290\, Ansys Corporation\, 9000 Virginia Manor Road\, Beltsville\, Marylan d\, United States\, 20705\, Virtual: https://events.vtools.ieee.org/m/5622 25 LOCATION:Room: Suite 290\, Ansys Corporation\, 9000 Virginia Manor Road\, B eltsville\, Maryland\, United States\, 20705\, Virtual: https://events.vto ols.ieee.org/m/562225 ORGANIZER:sandra.hyland@ieee.org SEQUENCE:59 SUMMARY:Improving Integrated Circuit Advanced Packaging Manufacturability w ith Thermomechanical Simulation URL;VALUE=URI:https://events.vtools.ieee.org/m/562225 X-ALT-DESC:Description: <br /><p class="MsoNormal">High-tech applications l ike autonomous driving\, 5G communication\, and especially artificial inte lligence and machine learning are driving the semiconductor industry to in crease microchip complexity and processing power more than ever. At the sa me time\, Moore&rsquo\;s Law\, which postulates that the number of transis tors in an integrated circuit doubles every two years and has roughly held since 1975\, is nearing its physical limit. As a result\, the electronics industry has moved towards advanced packaging solutions in the past decad e.</p>\n<p class="MsoNormal">Broadly\, advanced packaging refers to incorp orating multiple chips within a single electronic component\, often utiliz ing heterogeneous integration\, meaning the different chips within the pac kage have different functions. Additionally\, advanced packaging typically includes some degree of vertical stacking among the multiple chips. Stack ed structures reduce interconnect length by orders of magnitude\, leading to higher bandwidths\, capacities\, and data rates.</p>\n<p class="MsoNorm al">While these stacked features are extremely powerful from an electrical perspective\, they are also extremely complex from a structural and mater ial perspective. A single advanced package will often include silicon chip s\, a silicon or glass interposer\, and a glass fiber-reinforced organic s ubstrate all attached to each other with various solder and copper interco nnects. The total interconnect count can easily be in the hundreds of thou sands\, and the smallest interconnects can scale down several orders of ma gnitude from the overall package size. The whole package may then be cover ed with a protective polymer overmold or utilize a copper or steel stiffen er or lid.</p>\n<p class="MsoNormal">These packages require complex fabric ation processes involving several high-temperature events like multiple so lder reflows\, copper interconnect annealing\, and polymer cures. The vari ation in Young&rsquo\;s Modulus and coefficient of thermal expansion (CTE) throughout the structure can create stress concentrations that fracture i nterconnects across dissimilar materials during these many manufacturing-r elated temperature excursions. Furthermore\, even if the advanced package can be fabricated completely without issue\, soldering it to a circuit boa rd presents a potential problem. The CTE mismatches within the package can warp the package enough to create soldering defects during board-level re flow.</p>\n<p class="MsoNormal">The rapidly evolving nature of advanced pa ckaging\, the extreme number of interconnects within a single package\, an d the high production cost of cutting-edge semiconductors demand that simu lation play a role in evaluating the manufacturability of novel advanced p ackage designs. This presentation will overview key manufacturing processe s that can be evaluated with thermomechanical FEA for an advanced package design. It will also investigate strategies for dealing with modeling comp lications specific to advanced packages\, including how to address interco nnect scaling issues with layer simplification and submodeling and when to consider temperature-dependent and nonlinear material properties.</p><br /><br />Agenda: <br /><ul>\n<li>\n<div role="presentation">\n<p>&nbsp\;</p >\n<table style="border-collapse: collapse\; width: 52.4659%\;" border="1" ><colgroup><col style="width: 26.6388%\;"><col style="width: 73.3449%\;">< /colgroup>\n<tbody>\n<tr>\n<td>5:30 - 6:00 pm</td>\n<td>Gather and introdu ctions</td>\n</tr>\n<tr>\n<td>6:00 - 6:45 pm</td>\n<td>Ansys lab tour and electronics capabilities overview</td>\n</tr>\n<tr>\n<td>6:45 - 7:30 pm</t d>\n<td>Ansys speaker presentation</td>\n</tr>\n<tr>\n<td>7:30 pm</td>\n<t d>Wrap-up</td>\n</tr>\n</tbody>\n</table>\n</div>\n</li>\n</ul> END:VEVENT END:VCALENDAR