BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:America/Los_Angeles BEGIN:DAYLIGHT DTSTART:20260308T030000 TZOFFSETFROM:-0800 TZOFFSETTO:-0700 RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3 TZNAME:PDT END:DAYLIGHT BEGIN:STANDARD DTSTART:20261101T010000 TZOFFSETFROM:-0700 TZOFFSETTO:-0800 RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11 TZNAME:PST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20260626T162655Z UID:C1EF8B88-2632-486A-B481-459DC0416DE8 DTSTART;TZID=America/Los_Angeles:20260806T160000 DTEND;TZID=America/Los_Angeles:20260806T170000 DESCRIPTION:[]\n\nAs AI\, high-performance computing\, and heterogeneous in tegration continue to scale\, advanced packaging is facing growing interco nnect challenges across redistribution layers\, IC substrates\, HDI boards \, silicon vias\, and emerging glass-core platforms. Higher bandwidth and larger package form factors require finer wiring\, smaller vias\, higher f an-out density\, and more reliable vertical interconnects. In this context \, copper seed formation and via metallization are becoming increasingly i mportant bottlenecks for next-generation package and substrate scaling.\nC onventional copper deposition technologies\, including physical vapor depo sition\, electroless plating\, and electroplating\, each play essential ro les in today’s manufacturing flows. However\, as via structures become s maller\, deeper\, rougher\, or higher in aspect ratio\, limitations such a s step coverage\, liquid circulation\, process uniformity\, and seed-layer continuity become more difficult to manage. These challenges are especial ly relevant across multiple interconnect layers\, including motherboard HD I PCBs\, IC substrates\, RDL\, memory and interposer silicon vias\, and Si BEOL metal\, etc.\nThis presentation will introduce Nano Copper Depositio n as a solution family for AI-era interconnect scaling. The talk will cove r DeepVia™ HDI for high-aspect-ratio via metallization in motherboard HD I PCBs\, DS-SAP™ for resolving the trade-off between thin surface seed l ayers and robust via coverage in IC substrates\, and other applications su ch as Dual Seed Damascene for fine and high-aspect-ratio damascene structu res in BEOL and RDL applications\, and DeepVia™ Silicon for memory and i nterposer silicon vias. The discussion will highlight how these approaches can support higher I/O density\, improved escape routing\, reduced layer- count dependency\, and broader process flexibility for next-generation adv anced packaging.\n\nSpeaker(s): Shinya Shimizu\, \n\nVirtual: https://even ts.vtools.ieee.org/m/565310 LOCATION:Virtual: https://events.vtools.ieee.org/m/565310 ORGANIZER:p.wesling@ieee.org SEQUENCE:0 SUMMARY:Dual Seed Semi-Additive and Damascene Processes: Enabling Fine-Pitc h Interconnects for Advanced Packaging URL;VALUE=URI:https://events.vtools.ieee.org/m/565310 X-ALT-DESC:Description: <br /><p><img style="float: right\;" src="https://e vents.vtools.ieee.org/vtools_ui/media/display/4b6cfa83-508f-46c4-ad91-55b6 05d869d0" alt="" width="468" height="234"></p>\n<p>&nbsp\; &nbsp\; &nbsp\; As AI\, high-performance computing\, and heterogeneous integration continu e to scale\, advanced packaging is facing growing interconnect challenges across redistribution layers\, IC substrates\, HDI boards\, silicon vias\, and emerging glass-core platforms. Higher bandwidth and larger package fo rm factors require finer wiring\, smaller vias\, higher fan-out density\, and more reliable vertical interconnects. In this context\, copper seed fo rmation and via metallization are becoming increasingly important bottlene cks for next-generation package and substrate scaling.<br>&nbsp\; &nbsp\; &nbsp\;Conventional copper deposition technologies\, including physical va por deposition\, electroless plating\, and electroplating\, each play esse ntial roles in today&rsquo\;s manufacturing flows. However\, as via struct ures become smaller\, deeper\, rougher\, or higher in aspect ratio\, limit ations such as step coverage\, liquid circulation\, process uniformity\, a nd seed-layer continuity become more difficult to manage. These challenges are especially relevant across multiple interconnect layers\, including m otherboard HDI PCBs\, IC substrates\, RDL\, memory and interposer silicon vias\, and Si BEOL metal\, etc.<br>&nbsp\; &nbsp\; &nbsp\;This presentatio n will introduce Nano Copper Deposition as a solution family for AI-era in terconnect scaling. The talk will cover DeepVia&trade\; HDI for high-aspec t-ratio via metallization in motherboard HDI PCBs\, DS-SAP&trade\; for res olving the trade-off between thin surface seed layers and robust via cover age in IC substrates\, and other applications such as Dual Seed Damascene for fine and high-aspect-ratio damascene structures in BEOL and RDL applic ations\, and DeepVia&trade\; Silicon for memory and interposer silicon via s. The discussion will highlight how these approaches can support higher I /O density\, improved escape routing\, reduced layer-count dependency\, an d broader process flexibility for next-generation advanced packaging.</p> END:VEVENT END:VCALENDAR