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VERSION:2.0
PRODID:IEEE vTools.Events//EN
CALSCALE:GREGORIAN
BEGIN:VTIMEZONE
TZID:Asia/Kolkata
BEGIN:STANDARD
DTSTART:19451014T230000
TZOFFSETFROM:+0630
TZOFFSETTO:+0530
TZNAME:IST
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BEGIN:VEVENT
DTSTAMP:20260710T090744Z
UID:64409E7C-B60A-47E7-9A53-9D96002E4383
DTSTART;TZID=Asia/Kolkata:20260703T110000
DTEND;TZID=Asia/Kolkata:20260703T130000
DESCRIPTION:The IEEE CEDA Student Branch Chapter\, Nitte Meenakshi Institut
 e of Technology (NMIT)\, in association with the IEEE CEDA Bangalore Chapt
 er\, is organizing an IEEE CEDA Distinguished Talk titled “Physical Desi
 gn: From Past to Future” on 3 July 2026.\n\nThis insightful session will
  explore the evolution of physical design in microelectronics\, from early
  manual layout techniques used in microprocessor design to modern automate
 d layout generation methodologies. The talk will highlight the role of phy
 sical design automation in optimizing transistor layouts\, reducing power 
 consumption\, and advancing semiconductor technology.\n\n[]\n\nSpeaker(s):
  Ricardo Reis\n\nDr. APJ Abdul Kalam Seminar Hall\, Nitte Meenakshi Instit
 ute of Technology\, Bengaluru\, Karnataka\, India\, 560064
LOCATION:Dr. APJ Abdul Kalam Seminar Hall\, Nitte Meenakshi Institute of Te
 chnology\, Bengaluru\, Karnataka\, India\, 560064
ORGANIZER:avamsikrishna@ieee.org
SEQUENCE:10
SUMMARY:IEEE CEDA Distinguished Talk — “Physical Design: From Past to F
 uture”
URL;VALUE=URI:https://events.vtools.ieee.org/m/566044
X-ALT-DESC:Description: &lt;br /&gt;&lt;p class=&quot;PDq2pG_selectionAnchorContainer&quot; da
 ta-start=&quot;323&quot; data-end=&quot;640&quot;&gt;The IEEE CEDA Student Branch Chapter\, Nitte
  Meenakshi Institute of Technology (NMIT)\, in association with the IEEE C
 EDA Bangalore Chapter\, is organizing an IEEE CEDA Distinguished Talk titl
 ed &lt;strong data-start=&quot;540&quot; data-end=&quot;582&quot;&gt;&amp;ldquo\;Physical Design: From P
 ast to Future&amp;rdquo\;&lt;/strong&gt; on &lt;strong data-start=&quot;586&quot; data-end=&quot;601&quot;&gt;
 3 July 2026&lt;/strong&gt;.&lt;/p&gt;\n&lt;p data-start=&quot;642&quot; data-end=&quot;1054&quot;&gt;This insigh
 tful session will explore the evolution of physical design in microelectro
 nics\, from early manual layout techniques used in microprocessor design t
 o modern automated layout generation methodologies. The talk will highligh
 t the role of physical design automation in optimizing transistor layouts\
 , reducing power consumption\, and advancing semiconductor technology.&lt;/p&gt;
 \n&lt;p style=&quot;text-align: center\;&quot; data-start=&quot;642&quot; data-end=&quot;1054&quot;&gt;&lt;img sr
 c=&quot;https://events.vtools.ieee.org/vtools_ui/media/display/f9d73a0a-d1d0-4a
 be-bef8-3ee699ab0138&quot; alt=&quot;&quot; width=&quot;500&quot; height=&quot;707&quot;&gt;&lt;/p&gt;\n&lt;table style=&quot;
 border-collapse: collapse\; width: 100%\;&quot; border=&quot;1&quot;&gt;&lt;colgroup&gt;&lt;col style
 =&quot;width: 33.3009%\;&quot;&gt;&lt;col style=&quot;width: 33.3009%\;&quot;&gt;&lt;col style=&quot;width: 33.
 3009%\;&quot;&gt;&lt;/colgroup&gt;\n&lt;tbody&gt;\n&lt;tr&gt;\n&lt;td&gt;&lt;img src=&quot;https://events.vtools.i
 eee.org/vtools_ui/media/display/c322c5eb-66b6-4438-99c8-98697603e026&quot; widt
 h=&quot;330&quot; height=&quot;247&quot;&gt;&lt;/td&gt;\n&lt;td&gt;&lt;img src=&quot;https://events.vtools.ieee.org/v
 tools_ui/media/display/1d305224-c2fe-4d29-ab5e-97ecbf2a4bcf&quot; width=&quot;330&quot; h
 eight=&quot;242&quot;&gt;&lt;/td&gt;\n&lt;td&gt;&lt;img src=&quot;https://events.vtools.ieee.org/vtools_ui/
 media/display/01cebc60-4f71-46bf-8c4b-6b57dcdb552f&quot; width=&quot;330&quot; height=&quot;19
 1&quot;&gt;&lt;/td&gt;\n&lt;/tr&gt;\n&lt;/tbody&gt;\n&lt;/table&gt;
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