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TZID:Asia/Kolkata
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DTSTART:19451014T230000
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BEGIN:VEVENT
DTSTAMP:20260706T173342Z
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DTSTART;TZID=Asia/Kolkata:20260502T200000
DTEND;TZID=Asia/Kolkata:20260502T210000
DESCRIPTION:The IEEE Council on Electronic Design Automation (CEDA) Bangalo
 re Chapter\, in collaboration with the IEEE Solid-State Circuits Society (
 SSCS) Santa Clara Valley Section\, is pleased to present another session i
 n the IEEE CEDA Industry Insights Series.\n\nThis webinar\, &quot;Functional Ve
 rification of RTL Digital Designs: Crux &amp; Craft\,&quot; explores one of the mos
 t critical aspects of modern digital IC design—ensuring that RTL designs
  function correctly before fabrication. The session will cover the fundame
 ntals of RTL functional verification\, industry methodologies\, verificati
 on planning\, common challenges\, and practical approaches adopted in toda
 y&#39;s semiconductor industry.\n\nThe talk will be delivered by Dr. Ananthara
 j Thalaimalai Varnaraj\, Design Verification Leader – GPU Hardware\, Sam
 sung Austin Research and Development Center (SARC) and Advanced Computing 
 Lab (ACL)\, San Jose\, California. Drawing from extensive experience in GP
 U hardware verification\, Dr. Varnaraj will share practical insights into 
 verification strategies\, industry workflows\, and the evolving role of ve
 rification engineers in the semiconductor ecosystem.\n\nWhether you are a 
 student preparing for a career in VLSI\, an academic\, or an industry prof
 essional looking to deepen your understanding of digital design verificati
 on\, this webinar offers valuable knowledge directly from an experienced v
 erification leader.\n\nSpeaker\n\nDr. Anantharaj Thalaimalai Varnaraj\nDes
 ign Verification Leader – GPU Hardware\nSamsung Austin Research and Deve
 lopment Center (SARC) &amp; Advanced Computing Lab (ACL)\, San Jose\, Californ
 ia\n\n[]\n\nVirtual: https://events.vtools.ieee.org/m/566716
LOCATION:Virtual: https://events.vtools.ieee.org/m/566716
ORGANIZER:avamsikrishna@ieee.org
SEQUENCE:5
SUMMARY:IEEE CEDA Industry Insights Series | Functional Verification of RTL
  Digital Designs: Crux &amp; Craft
URL;VALUE=URI:https://events.vtools.ieee.org/m/566716
X-ALT-DESC:Description: &lt;br /&gt;&lt;p class=&quot;PDq2pG_selectionAnchorContainer&quot; da
 ta-start=&quot;184&quot; data-end=&quot;446&quot;&gt;The &lt;strong data-start=&quot;188&quot; data-end=&quot;261&quot;&gt;
 IEEE Council on Electronic Design Automation (CEDA) Bangalore Chapter&lt;/str
 ong&gt;\, in collaboration with the &lt;strong data-start=&quot;289&quot; data-end=&quot;360&quot;&gt;I
 EEE Solid-State Circuits Society (SSCS) Santa Clara Valley Section&lt;/strong
 &gt;\, is pleased to present another session in the &lt;strong data-start=&quot;407&quot; 
 data-end=&quot;445&quot;&gt;IEEE CEDA Industry Insights Series&lt;/strong&gt;.&lt;/p&gt;\n&lt;p data-s
 tart=&quot;448&quot; data-end=&quot;870&quot;&gt;This webinar\, &lt;strong data-start=&quot;462&quot; data-end
 =&quot;529&quot;&gt;&quot;Functional Verification of RTL Digital Designs: Crux &amp;amp\; Craft\
 ,&quot;&lt;/strong&gt; explores one of the most critical aspects of modern digital IC
  design&amp;mdash\;ensuring that RTL designs function correctly before fabrica
 tion. The session will cover the fundamentals of RTL functional verificati
 on\, industry methodologies\, verification planning\, common challenges\, 
 and practical approaches adopted in today&#39;s semiconductor industry.&lt;/p&gt;\n&lt;
 p data-start=&quot;872&quot; data-end=&quot;1336&quot;&gt;The talk will be delivered by &lt;strong d
 ata-start=&quot;902&quot; data-end=&quot;941&quot;&gt;Dr. Anantharaj Thalaimalai Varnaraj&lt;/strong
 &gt;\, &lt;strong data-start=&quot;943&quot; data-end=&quot;1098&quot;&gt;Design Verification Leader &amp;n
 dash\; GPU Hardware\, Samsung Austin Research and Development Center (SARC
 ) and Advanced Computing Lab (ACL)\, San Jose\, California&lt;/strong&gt;. Drawi
 ng from extensive experience in GPU hardware verification\, Dr. Varnaraj w
 ill share practical insights into verification strategies\, industry workf
 lows\, and the evolving role of verification engineers in the semiconducto
 r ecosystem.&lt;/p&gt;\n&lt;p data-start=&quot;1338&quot; data-end=&quot;1594&quot;&gt;Whether you are a s
 tudent preparing for a career in VLSI\, an academic\, or an industry profe
 ssional looking to deepen your understanding of digital design verificatio
 n\, this webinar offers valuable knowledge directly from an experienced ve
 rification leader.&lt;/p&gt;\n&lt;h3 data-section-id=&quot;yffual&quot; data-start=&quot;1596&quot; dat
 a-end=&quot;1607&quot;&gt;Speaker&lt;/h3&gt;\n&lt;p data-start=&quot;1608&quot; data-end=&quot;1800&quot;&gt;&lt;strong da
 ta-start=&quot;1608&quot; data-end=&quot;1647&quot;&gt;Dr. Anantharaj Thalaimalai Varnaraj&lt;/stron
 g&gt;&lt;br data-start=&quot;1647&quot; data-end=&quot;1650&quot;&gt;Design Verification Leader &amp;ndash\
 ; GPU Hardware&lt;br data-start=&quot;1691&quot; data-end=&quot;1694&quot;&gt;Samsung Austin Researc
 h and Development Center (SARC) &amp;amp\; Advanced Computing Lab (ACL)\, San 
 Jose\, California&lt;/p&gt;\n&lt;p style=&quot;text-align: center\;&quot; data-start=&quot;1608&quot; d
 ata-end=&quot;1800&quot;&gt;&lt;img src=&quot;https://events.vtools.ieee.org/vtools_ui/media/di
 splay/f9cd854e-a8f9-44a1-ace0-37258e728329&quot; alt=&quot;&quot; width=&quot;531&quot; height=&quot;664
 &quot;&gt;&lt;/p&gt;
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