BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:America/Guatemala BEGIN:STANDARD DTSTART:20060930T230000 TZOFFSETFROM:-0500 TZOFFSETTO:-0600 TZNAME:CST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20260707T060529Z UID:B7C9DE26-CA44-43CD-B393-684D443E8803 DTSTART;TZID=America/Guatemala:20260717T121000 DTEND;TZID=America/Guatemala:20260717T163000 DESCRIPTION:PART I: The Road to Gate-All-Around CMOS (07/17 -- 12:10PM )\nD espite the much debated end of Moore's Law\, CMOS scaling still maintains economic relevance with 2nm gate-all-around SoCs anticipated in the coming quarters. Area scaling extensively driven by design/technology innovation s co-optimized for primarily logic scaling continue to offer compelling no de-to-node power\, performance\, area\, and cost benefits. In this tutoria l\, we will start with a walk through memory lane\, recounting a brief his tory of transistor evolution to motivate the migration from the planar MOS FET to the fully depleted FinFET. We will summarize the key process techno logy elements that have enabled the finFET CMOS nodes\, highlighting the r esulting technology characteristics and challenges. This will set the stag e for transitioning to the nanoribbon gate-all-around (GAA) transistor arc hitecture and unveiling the magic of how these devices are fabricated.\n\n Part II: The Road to Gate-All-Around and Its Impact on Analog Design (07/1 7 -- 2:30PM )\nEmbrace the technology – the essence of how analog design has adapted and thrived throughout decades of increasingly unfriendly CMO S scaling. This presentation will cover the impact of advanced CMOS on ana log design\, and examples of the creativity of analog designers to preserv e and extend the performance of traditional analog functions. We will fina lly take a look at technologies on the horizon and suggest how they will i mpact the future of analog design based on the challenges that CMOS scalin g has imposed. To address the growing effort required for analog/mixed-sig nal design\, we will cover design strategies on how analog design has adap ted and thrived through decades of increasingly unfriendly scaling\, inclu ding the migration to heterogeneous integration.\n\nSpeaker(s): \, Alvin\n \nAgenda: \nPART I (07/17 -- 12:10PM):\n\nThe Road to Gate-All-Around CMOS ( 12:10-1:30PM )\n\nQ&A ( 1:30-2:00PM )\n\nBreak\, complimentary snacks/d rinks.( 2:00-2:30PM )\n\nPART II (07/17 -- 2:30PM):\n\nThe Road to Gate-Al l-Around CMOS ( 2:30-4.00PM )\n\nQ&A ( 4.00-4.30PM )\n\nBreak\, compliment ary snacks/drinks.( 4.30-5:00PM )\n\nRoom: 1NEO\, Bldg: RR5\, 1600 Rio Ran cho Blvd SE\, Rio Rancho\, New Mexico\, United States\, 87124\, Virtual: h ttps://events.vtools.ieee.org/m/566775 LOCATION:Room: 1NEO\, Bldg: RR5\, 1600 Rio Rancho Blvd SE\, Rio Rancho\, Ne w Mexico\, United States\, 87124\, Virtual: https://events.vtools.ieee.org /m/566775 ORGANIZER:rsalazar@ieee.org SEQUENCE:81 SUMMARY:IEEE Albuquerque SSCS/EDS Joint Chapter: Inaugural Talk URL;VALUE=URI:https://events.vtools.ieee.org/m/566775 X-ALT-DESC:Description: <br /><p><span style="color: rgb(0\, 0\, 0)\;"><spa n style="font-size: 18pt\; font-family: Aptos\; font-style: italic\;">PART I: </span><span style="font-size: 18pt\; font-family: Aptos\; font-weight : bold\; font-style: italic\;">The Road to Gate-All-Around CMOS </span><sp an style="font-size: 18pt\; font-family: Aptos\; font-style: italic\;">(07 /17 -- 12:10PM )</span><span style="font-size: 18pt\; font-family: Aptos\; font-weight: bold\; font-style: italic\;"><br></span><span style="font-si ze: 10pt\; font-family: Aptos\;">Despite the </span><span style="font-size : 10pt\; font-family: Aptos\;">much debated</span><span style="font-size: 10pt\; font-family: Aptos\;"> end of Moore's Law\, CMOS scaling still main tains economic relevance with 2nm gate-all-around SoCs anticipated in the coming quarters. Area scaling extensively driven by design/technology inno vations co-optimized for primarily logic scaling continue to offer compell ing node-to-node power\, performance\, area\, and cost benefits. In this t utorial\, we will start with a </span><span style="font-size: 10pt\; font- family: Aptos\;">walk through</span><span style="font-size: 10pt\; font-fa mily: Aptos\;"> memory lane\, recounting a brief history of transistor evo lution to motivate the migration from the planar MOSFET to the fully deple ted </span><span style="font-size: 10pt\; font-family: Aptos\;">FinFET</sp an><span style="font-size: 10pt\; font-family: Aptos\;">. We will summariz e the key process technology elements that have enabled the </span><span s tyle="font-size: 10pt\; font-family: Aptos\;">finFET</span><span style="fo nt-size: 10pt\; font-family: Aptos\;"> CMOS nodes\, highlighting the resul ting technology characteristics and challenges. This will set the stage fo r transitioning to the nanoribbon gate-all-around (GAA) transistor archite cture and unveiling the magic of how these devices are fabricated.</span>< /span></p>\n<p><span style="color: rgb(0\, 0\, 0)\;"><span style="font-siz e: 18pt\; font-family: Aptos\; font-weight: bold\; font-style: italic\;">< br></span><span style="font-size: 18pt\; font-family: Aptos\; font-style: italic\;">Part II: </span><span style="font-size: 18pt\; font-family: Apto s\; font-weight: bold\; font-style: italic\;">The Road to Gate-All-Around and Its Impact on Analog Design </span><span style="font-size: 18pt\; font -family: Aptos\; font-style: italic\;">(07/17 </span><span style="font-siz e: 18pt\; font-family: Aptos\; font-style: italic\;">-</span><span style=" font-size: 18pt\; font-family: Aptos\; font-style: italic\;">-</span><span style="font-size: 18pt\; font-family: Aptos\; font-style: italic\;"> 2:30 PM </span><span style="font-size: 18pt\; font-family: Aptos\; font-style: italic\;">)</span><span style="font-size: 18pt\; font-family: Aptos\;"><br ></span><span style="font-size: 10pt\; font-family: Aptos\;">Embrace the t echnology &ndash\; the essence of how analog design has adapted and thrive d throughout decades of increasingly unfriendly CMOS scaling.<span style=" mso-spacerun: yes\;">&nbsp\; </span>This presentation will cover the impac t of advanced CMOS on analog design\, and examples of the creativity of an alog designers to preserve and extend the performance of traditional analo g functions. We will finally </span><span style="font-size: 10pt\; font-fa mily: Aptos\;">take a look</span><span style="font-size: 10pt\; font-famil y: Aptos\;"> at technologies on the horizon and suggest how they will impa ct the future of analog design based on<span style="mso-spacerun: yes\;">& nbsp\; </span></span><span style="font-size: 10pt\; font-family: Aptos\;"> the challenges that CMOS scaling has </span></span><span style="font-size: 10.0pt\; font-family: Aptos\; mso-ascii-font-family: Aptos\; mso-fareast- font-family: 'Helvetica Neue'\; mso-bidi-font-family: 'Helvetica Neue'\; m so-fareast-theme-font: major-fareast\; mso-bidi-theme-font: major-bidi\; c olor: white\; mso-color-index: 0\; mso-font-kerning: 12.0pt\; language: en -US\; mso-style-textfill-type: solid\; mso-style-textfill-fill-themecolor: background1\; mso-style-textfill-fill-color: white\; mso-style-textfill-f ill-alpha: 100.0%\;"><span style="color: rgb(0\, 0\, 0)\;">imposed. To add ress the growing effort required for analog/mixed-signal design\, we will cover design strategies on how analog design has adapted and thrived throu gh decades of increasingly unfriendly scaling\, including the migration to </span></span><span style="color: rgb(0\, 0\, 0)\;"><span style="font-siz e: 10pt\; font-family: Aptos\; font-weight: bold\; font-style: italic\;">h eterogeneous integration</span><span style="font-size: 10pt\; font-family: Aptos\;">.</span></span></p><br /><br />Agenda: <br /><p><span style="col or: rgb(0\, 0\, 0)\;"><span style="font-size: 18pt\; font-family: Aptos\; font-style: italic\;">PART I (07/17 -- 12:10PM):&nbsp\;</span></span></p>\ n<p><span style="color: rgb(0\, 0\, 0)\;"><span style="font-size: 18pt\; f ont-family: Aptos\; font-weight: bold\; font-style: italic\;">The Road to Gate-All-Around CMOS&nbsp\;</span><span style="font-size: 18pt\; font-fami ly: Aptos\; font-style: italic\;">( 12:10-1:30PM )</span></span></p>\n<p>< span style="color: rgb(0\, 0\, 0)\;"><span style="font-size: 18pt\; font-f amily: Aptos\; font-style: italic\;"><span style="font-size: 18pt\; font-f amily: Aptos\; font-weight: bold\; font-style: italic\;">Q&amp\;A </span>( 1:30-2:00PM )</span></span></p>\n<p><span style="color: rgb(0\, 0\, 0)\;" ><span style="font-size: 18pt\; font-family: Aptos\; font-style: italic\;" ><span style="font-size: 18pt\; font-family: Aptos\; font-weight: bold\; f ont-style: italic\;">Break\, complimentary snacks/drinks.</span>( 2:00-2:3 0PM )</span></span></p>\n<p>&nbsp\;</p>\n<p><span style="color: rgb(0\, 0\ , 0)\;"><span style="font-size: 18pt\; font-family: Aptos\; font-style: it alic\;">PART II (07/17 -- 2:30PM):&nbsp\;</span></span></p>\n<p><span styl e="color: rgb(0\, 0\, 0)\;"><span style="font-size: 18pt\; font-family: Ap tos\; font-weight: bold\; font-style: italic\;">The Road to Gate-All-Aroun d CMOS&nbsp\;</span><span style="font-size: 18pt\; font-family: Aptos\; fo nt-style: italic\;">( 2:30-4.00PM )</span></span></p>\n<p><span style="col or: rgb(0\, 0\, 0)\;"><span style="font-size: 18pt\; font-family: Aptos\; font-style: italic\;"><span style="font-size: 18pt\; font-family: Aptos\; font-weight: bold\; font-style: italic\;">Q&amp\;A </span>( 4.00-4.30PM )< /span></span></p>\n<p><span style="color: rgb(0\, 0\, 0)\;"><span style="f ont-size: 18pt\; font-family: Aptos\; font-style: italic\;"><span style="f ont-size: 18pt\; font-family: Aptos\; font-weight: bold\; font-style: ital ic\;">Break\, complimentary snacks/drinks.</span>( 4.30-5:00PM )</span></s pan></p> END:VEVENT END:VCALENDAR