BEGIN:VCALENDAR
VERSION:2.0
PRODID:IEEE vTools.Events//EN
CALSCALE:GREGORIAN
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TZID:Asia/Kolkata
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DTSTART:19451014T230000
TZOFFSETFROM:+0630
TZOFFSETTO:+0530
TZNAME:IST
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BEGIN:VEVENT
DTSTAMP:20260708T151720Z
UID:7026B074-EA2E-4A37-8B30-127961B05871
DTSTART;TZID=Asia/Kolkata:20260427T100000
DTEND;TZID=Asia/Kolkata:20260427T123000
DESCRIPTION:The logic design competition was conducted on 27 April 2026 fro
 m 10:00 AM to 12:30 PM as a part of &quot;PAETRIX &quot; a four day National level t
 ech summit. A total of 4 teams participated in the competition including t
 eam from other college also\, making the competition more diverse and comp
 etitive.\n\nThere were 5 rounds\, round 1 was technical quiz\, round 2 was
  to find the output of the given circuit\, round 3 was to solve the given 
 Boolean expression\, round 5 was to correct the error in the given circuit
  and final round was to build a circuit and show the output.\n\nJudging wa
 s based on marks given in each rounds.\n\nWinners:Team Ec royals - PA coll
 ege of engineering mangalore\n\nRunners:Team SDMIT- ujire\n\nThe prizes we
 re awarded by Dr. Asiya hazareena and prof. Mohammed Hussain. The event su
 ccessfully enhanced the students practical knowledge on logic gates and in
 creased their confidence.\n\nThe event was coordinated by Faculty coordina
 tor prof. Arshiya Nazneen N Z(ECE)along with student coordinators Mohammed
  Zohan (ECE) and Mohammed Sinan (ECE).\n\n[]	[]\n[]	[]\n\nVLSI Lab\, Depar
 tment of ECE\, P. A. College of Engineering (PACE)\, Near Mangalore Univer
 sity\, Kudla\, Kalarangala\, Mangalore\, Karnataka\, India\, 574153
LOCATION:VLSI Lab\, Department of ECE\, P. A. College of Engineering (PACE)
 \, Near Mangalore University\, Kudla\, Kalarangala\, Mangalore\, Karnataka
 \, India\, 574153
ORGANIZER:avamsikrishna@ieee.org
SEQUENCE:13
SUMMARY:PAETRIX Logic Design
URL;VALUE=URI:https://events.vtools.ieee.org/m/567053
X-ALT-DESC:Description: &lt;br /&gt;&lt;p class=&quot;MsoNormal&quot; style=&quot;text-align: justi
 fy\; margin: 12.0pt 0cm 12.0pt 0cm\;&quot;&gt;&lt;span lang=&quot;EN&quot; style=&quot;font-size: 14
 .0pt\; line-height: 107%\;&quot;&gt;The logic design competition was conducted on 
 27 April 2026 from 10:00 AM to 12:30 PM as a part of &quot;PAETRIX &quot; a four day
  National level tech summit. A total of 4 teams participated in the compet
 ition including team from other college also\, making the competition more
  diverse and competitive.&lt;/span&gt;&lt;/p&gt;\n&lt;p class=&quot;MsoNormal&quot; style=&quot;text-ali
 gn: justify\; margin: 12.0pt 0cm 12.0pt 0cm\;&quot;&gt;&lt;span lang=&quot;EN&quot; style=&quot;font
 -size: 14.0pt\; line-height: 107%\;&quot;&gt;There were 5 rounds\, round 1 was tec
 hnical quiz\, round 2 was to find the output of the given circuit\, round 
 3 was to solve the given Boolean expression\, round 5 was to correct the e
 rror in the given circuit and final round was to build a circuit and show 
 the output.&lt;/span&gt;&lt;/p&gt;\n&lt;p class=&quot;MsoNormal&quot; style=&quot;text-align: justify\; 
 margin: 12.0pt 0cm 12.0pt 0cm\;&quot;&gt;&lt;span lang=&quot;EN&quot; style=&quot;font-size: 14.0pt\
 ; line-height: 107%\;&quot;&gt;Judging was based on marks given in each rounds.&lt;/s
 pan&gt;&lt;/p&gt;\n&lt;p class=&quot;MsoNormal&quot; style=&quot;text-align: justify\; margin: 12.0pt
  0cm 12.0pt 0cm\;&quot;&gt;&lt;span lang=&quot;EN&quot; style=&quot;font-size: 14.0pt\; line-height:
  107%\;&quot;&gt;Winners:Team Ec royals - PA college of engineering mangalore&lt;/spa
 n&gt;&lt;/p&gt;\n&lt;p class=&quot;MsoNormal&quot; style=&quot;text-align: justify\; margin: 12.0pt 0
 cm 12.0pt 0cm\;&quot;&gt;&lt;span lang=&quot;EN&quot; style=&quot;font-size: 14.0pt\; line-height: 1
 07%\;&quot;&gt;Runners:Team SDMIT- ujire&lt;/span&gt;&lt;/p&gt;\n&lt;p class=&quot;MsoNormal&quot; style=&quot;t
 ext-align: justify\; margin: 12.0pt 0cm 12.0pt 0cm\;&quot;&gt;&lt;span lang=&quot;EN&quot; styl
 e=&quot;font-size: 14.0pt\; line-height: 107%\;&quot;&gt;The prizes were awarded by Dr.
  Asiya hazareena and prof. Mohammed Hussain. The event successfully enhanc
 ed the students practical knowledge on logic gates and increased their con
 fidence.&lt;/span&gt;&lt;/p&gt;\n&lt;p class=&quot;MsoNormal&quot; style=&quot;text-align: justify\; mar
 gin: 12.0pt 0cm 12.0pt 0cm\;&quot;&gt;&lt;span lang=&quot;EN&quot; style=&quot;font-size: 14.0pt\; l
 ine-height: 107%\;&quot;&gt;The event was coordinated by Faculty coordinator prof.
  Arshiya Nazneen N Z(ECE)along with student coordinators Mohammed Zohan (E
 CE) and Mohammed Sinan (ECE).&lt;/span&gt;&lt;/p&gt;\n&lt;table style=&quot;border-collapse: c
 ollapse\; width: 100%\;&quot; border=&quot;1&quot;&gt;&lt;colgroup&gt;&lt;col style=&quot;width: 50%\;&quot;&gt;&lt;c
 ol style=&quot;width: 50%\;&quot;&gt;&lt;/colgroup&gt;\n&lt;tbody&gt;\n&lt;tr&gt;\n&lt;td style=&quot;text-align:
  center\;&quot;&gt;&lt;img src=&quot;https://events.vtools.ieee.org/vtools_ui/media/displa
 y/4ee3909a-4946-476d-948d-de8bc63c6ce5&quot; alt=&quot;&quot; width=&quot;500&quot; height=&quot;346&quot;&gt;&lt;/
 td&gt;\n&lt;td style=&quot;text-align: center\;&quot;&gt;&lt;img src=&quot;https://events.vtools.ieee
 .org/vtools_ui/media/display/ef20e800-3a28-4f90-b346-5161eeb9932f&quot; alt=&quot;&quot; 
 width=&quot;500&quot; height=&quot;250&quot;&gt;&lt;/td&gt;\n&lt;/tr&gt;\n&lt;tr&gt;\n&lt;td style=&quot;text-align: center
 \;&quot;&gt;&lt;img src=&quot;https://events.vtools.ieee.org/vtools_ui/media/display/9eb2e
 b88-1f6e-4084-84b1-4294e6b25714&quot; alt=&quot;&quot; width=&quot;500&quot; height=&quot;226&quot;&gt;&lt;/td&gt;\n&lt;t
 d style=&quot;text-align: center\;&quot;&gt;&lt;img src=&quot;https://events.vtools.ieee.org/vt
 ools_ui/media/display/911e88f4-72bc-41f0-9ab7-0a903384f489&quot; alt=&quot;&quot; width=&quot;
 300&quot; height=&quot;410&quot;&gt;&lt;/td&gt;\n&lt;/tr&gt;\n&lt;/tbody&gt;\n&lt;/table&gt;
END:VEVENT
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